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Merge branch 'add-si3474-pse-controller-driver'
Piotr Kubik says: ==================== Add Si3474 PSE controller driver From: Piotr Kubik <piotr.kubik@adtran.com> These patch series provide support for Skyworks Si3474 I2C Power Sourcing Equipment controller. Based on the TPS23881 driver code. Supported features of Si3474: - get port status, - get port power, - get port voltage, - enable/disable port power Signed-off-by: Piotr Kubik <piotr.kubik@adtran.com> ==================== Link: https://patch.msgid.link/6af537dc-8a52-4710-8a18-dcfbb911cf23@adtran.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Paolo Abeni
commit
84482586b2
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@ -0,0 +1,144 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/pse-pd/skyworks,si3474.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Skyworks Si3474 Power Sourcing Equipment controller
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maintainers:
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- Piotr Kubik <piotr.kubik@adtran.com>
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allOf:
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- $ref: pse-controller.yaml#
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properties:
|
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compatible:
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enum:
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- skyworks,si3474
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: main
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- const: secondary
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channels:
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description: The Si3474 is a single-chip PoE PSE controller managing
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8 physical power delivery channels. Internally, it's structured
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into two logical "Quads".
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Quad 0 Manages physical channels ('ports' in datasheet) 0, 1, 2, 3
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Quad 1 Manages physical channels ('ports' in datasheet) 4, 5, 6, 7.
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type: object
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additionalProperties: false
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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'^channel@[0-7]$':
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type: object
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additionalProperties: false
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properties:
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reg:
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maxItems: 1
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required:
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- reg
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required:
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- "#address-cells"
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- "#size-cells"
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required:
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- compatible
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- reg
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- pse-pis
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unevaluatedProperties: false
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examples:
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- |
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-pse@26 {
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compatible = "skyworks,si3474";
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reg-names = "main", "secondary";
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reg = <0x26>, <0x27>;
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channels {
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#address-cells = <1>;
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#size-cells = <0>;
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phys0_0: channel@0 {
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reg = <0>;
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};
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phys0_1: channel@1 {
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reg = <1>;
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};
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phys0_2: channel@2 {
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reg = <2>;
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};
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phys0_3: channel@3 {
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reg = <3>;
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};
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phys0_4: channel@4 {
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reg = <4>;
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};
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phys0_5: channel@5 {
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reg = <5>;
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};
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phys0_6: channel@6 {
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reg = <6>;
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};
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phys0_7: channel@7 {
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reg = <7>;
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};
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};
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pse-pis {
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#address-cells = <1>;
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#size-cells = <0>;
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pse_pi0: pse-pi@0 {
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reg = <0>;
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#pse-cells = <0>;
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pairset-names = "alternative-a", "alternative-b";
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pairsets = <&phys0_0>, <&phys0_1>;
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polarity-supported = "MDI-X", "S";
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vpwr-supply = <®_pse>;
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};
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pse_pi1: pse-pi@1 {
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reg = <1>;
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#pse-cells = <0>;
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pairset-names = "alternative-a", "alternative-b";
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pairsets = <&phys0_2>, <&phys0_3>;
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polarity-supported = "MDI-X", "S";
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vpwr-supply = <®_pse>;
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};
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pse_pi2: pse-pi@2 {
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reg = <2>;
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#pse-cells = <0>;
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pairset-names = "alternative-a", "alternative-b";
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pairsets = <&phys0_4>, <&phys0_5>;
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polarity-supported = "MDI-X", "S";
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vpwr-supply = <®_pse>;
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};
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pse_pi3: pse-pi@3 {
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reg = <3>;
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#pse-cells = <0>;
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pairset-names = "alternative-a", "alternative-b";
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pairsets = <&phys0_6>, <&phys0_7>;
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polarity-supported = "MDI-X", "S";
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vpwr-supply = <®_pse>;
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};
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};
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};
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};
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@ -32,6 +32,17 @@ config PSE_PD692X0
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To compile this driver as a module, choose M here: the
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module will be called pd692x0.
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config PSE_SI3474
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tristate "Si3474 PSE controller"
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depends on I2C
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help
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This module provides support for Si3474 regulator based Ethernet
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Power Sourcing Equipment.
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Only 4-pair PSE configurations are supported.
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To compile this driver as a module, choose M here: the
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module will be called si3474.
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config PSE_TPS23881
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tristate "TPS23881 PSE controller"
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depends on I2C
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@ -5,4 +5,5 @@ obj-$(CONFIG_PSE_CONTROLLER) += pse_core.o
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obj-$(CONFIG_PSE_REGULATOR) += pse_regulator.o
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obj-$(CONFIG_PSE_PD692X0) += pd692x0.o
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obj-$(CONFIG_PSE_SI3474) += si3474.o
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obj-$(CONFIG_PSE_TPS23881) += tps23881.o
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578
drivers/net/pse-pd/si3474.c
Normal file
578
drivers/net/pse-pd/si3474.c
Normal file
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@ -0,0 +1,578 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Driver for the Skyworks Si3474 PoE PSE Controller
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*
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* Chip Architecture & Terminology:
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*
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* The Si3474 is a single-chip PoE PSE controller managing 8 physical power
|
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* delivery channels. Internally, it's structured into two logical "Quads".
|
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*
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* Quad 0: Manages physical channels ('ports' in datasheet) 0, 1, 2, 3
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* Quad 1: Manages physical channels ('ports' in datasheet) 4, 5, 6, 7
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*
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* Each Quad is accessed via a separate I2C address. The base address range is
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* set by hardware pins A1-A4, and the specific address selects Quad 0 (usually
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* the lower/even address) or Quad 1 (usually the higher/odd address).
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* See datasheet Table 2.2 for the address mapping.
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*
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* While the Quads manage channel-specific operations, the Si3474 package has
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* several resources shared across the entire chip:
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* - Single RESETb input pin.
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* - Single INTb output pin (signals interrupts from *either* Quad).
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* - Single OSS input pin (Emergency Shutdown).
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* - Global I2C Address (0x7F) used for firmware updates.
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* - Global status monitoring (Temperature, VDD/VPWR Undervoltage Lockout).
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*
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* Driver Architecture:
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*
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* To handle the mix of per-Quad access and shared resources correctly, this
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* driver treats the entire Si3474 package as one logical device. The driver
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* instance associated with the primary I2C address (Quad 0) takes ownership.
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* It discovers and manages the I2C client for the secondary address (Quad 1).
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* This primary instance handles shared resources like IRQ management and
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* registers a single PSE controller device representing all logical PIs.
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* Internal functions route I2C commands to the appropriate Quad's i2c_client
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* based on the target channel or PI.
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*
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* Terminology Mapping:
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*
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* - "PI" (Power Interface): Refers to the logical PSE port as defined by
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* IEEE 802.3 (typically corresponds to an RJ45 connector). This is the
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* `id` (0-7) used in the pse_controller_ops.
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* - "Channel": Refers to one of the 8 physical power control paths within
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* the Si3474 chip itself (hardware channels 0-7). This terminology is
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* used internally within the driver to avoid confusion with 'ports'.
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* - "Quad": One of the two internal 4-channel management units within the
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* Si3474, each accessed via its own I2C address.
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*
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* Relationship:
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* - A 2-Pair PoE PI uses 1 Channel.
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* - A 4-Pair PoE PI uses 2 Channels.
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*
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* ASCII Schematic:
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*
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* +-----------------------------------------------------+
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* | Si3474 Chip |
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* | |
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* | +---------------------+ +---------------------+ |
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* | | Quad 0 | | Quad 1 | |
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* | | Channels 0, 1, 2, 3 | | Channels 4, 5, 6, 7 | |
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* | +----------^----------+ +-------^-------------+ |
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* | I2C Addr 0 | | I2C Addr 1 |
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* | +------------------------+ |
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* | (Primary Driver Instance) (Managed by Primary) |
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* | |
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* | Shared Resources (affect whole chip): |
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* | - Single INTb Output -> Handled by Primary |
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* | - Single RESETb Input |
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* | - Single OSS Input -> Handled by Primary |
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* | - Global I2C Addr (0x7F) for Firmware Update |
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* | - Global Status (Temp, VDD/VPWR UVLO) |
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* +-----------------------------------------------------+
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* | | | | | | | |
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* Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 (Physical Channels)
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*
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* Example Mapping (Logical PI to Physical Channel(s)):
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* * 2-Pair Mode (8 PIs):
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* PI 0 -> Ch 0
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* PI 1 -> Ch 1
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* ...
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* PI 7 -> Ch 7
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* * 4-Pair Mode (4 PIs):
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* PI 0 -> Ch 0 + Ch 1 (Managed via Quad 0 Addr)
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* PI 1 -> Ch 2 + Ch 3 (Managed via Quad 0 Addr)
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* PI 2 -> Ch 4 + Ch 5 (Managed via Quad 1 Addr)
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* PI 3 -> Ch 6 + Ch 7 (Managed via Quad 1 Addr)
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* (Note: Actual mapping depends on Device Tree and PORT_REMAP config)
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*/
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pse-pd/pse.h>
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#define SI3474_MAX_CHANS 8
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#define MANUFACTURER_ID 0x08
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#define IC_ID 0x05
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#define SI3474_DEVICE_ID (MANUFACTURER_ID << 3 | IC_ID)
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/* Misc registers */
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#define VENDOR_IC_ID_REG 0x1B
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#define TEMPERATURE_REG 0x2C
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#define FIRMWARE_REVISION_REG 0x41
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#define CHIP_REVISION_REG 0x43
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/* Main status registers */
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#define POWER_STATUS_REG 0x10
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#define PORT_MODE_REG 0x12
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#define DETECT_CLASS_ENABLE_REG 0x14
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/* PORTn Current */
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#define PORT1_CURRENT_LSB_REG 0x30
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/* PORTn Current [mA], return in [nA] */
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/* 1000 * ((PORTn_CURRENT_MSB << 8) + PORTn_CURRENT_LSB) / 16384 */
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#define SI3474_NA_STEP (1000 * 1000 * 1000 / 16384)
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/* VPWR Voltage */
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#define VPWR_LSB_REG 0x2E
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#define VPWR_MSB_REG 0x2F
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/* PORTn Voltage */
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#define PORT1_VOLTAGE_LSB_REG 0x32
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/* VPWR Voltage [V], return in [uV] */
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/* 60 * (( VPWR_MSB << 8) + VPWR_LSB) / 16384 */
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#define SI3474_UV_STEP (1000 * 1000 * 60 / 16384)
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/* Helper macros */
|
||||
#define CHAN_IDX(chan) ((chan) % 4)
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#define CHAN_BIT(chan) BIT(CHAN_IDX(chan))
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#define CHAN_UPPER_BIT(chan) BIT(CHAN_IDX(chan) + 4)
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#define CHAN_MASK(chan) (0x03U << (2 * CHAN_IDX(chan)))
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#define CHAN_REG(base, chan) ((base) + (CHAN_IDX(chan) * 4))
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||||
|
||||
struct si3474_pi_desc {
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u8 chan[2];
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bool is_4p;
|
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};
|
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|
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struct si3474_priv {
|
||||
struct i2c_client *client[2];
|
||||
struct pse_controller_dev pcdev;
|
||||
struct device_node *np;
|
||||
struct si3474_pi_desc pi[SI3474_MAX_CHANS];
|
||||
};
|
||||
|
||||
static struct si3474_priv *to_si3474_priv(struct pse_controller_dev *pcdev)
|
||||
{
|
||||
return container_of(pcdev, struct si3474_priv, pcdev);
|
||||
}
|
||||
|
||||
static void si3474_get_channels(struct si3474_priv *priv, int id,
|
||||
u8 *chan0, u8 *chan1)
|
||||
{
|
||||
*chan0 = priv->pi[id].chan[0];
|
||||
*chan1 = priv->pi[id].chan[1];
|
||||
}
|
||||
|
||||
static struct i2c_client *si3474_get_chan_client(struct si3474_priv *priv,
|
||||
u8 chan)
|
||||
{
|
||||
return (chan < 4) ? priv->client[0] : priv->client[1];
|
||||
}
|
||||
|
||||
static int si3474_pi_get_admin_state(struct pse_controller_dev *pcdev, int id,
|
||||
struct pse_admin_state *admin_state)
|
||||
{
|
||||
struct si3474_priv *priv = to_si3474_priv(pcdev);
|
||||
struct i2c_client *client;
|
||||
bool is_enabled;
|
||||
u8 chan0, chan1;
|
||||
s32 ret;
|
||||
|
||||
si3474_get_channels(priv, id, &chan0, &chan1);
|
||||
client = si3474_get_chan_client(priv, chan0);
|
||||
|
||||
ret = i2c_smbus_read_byte_data(client, PORT_MODE_REG);
|
||||
if (ret < 0) {
|
||||
admin_state->c33_admin_state =
|
||||
ETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN;
|
||||
return ret;
|
||||
}
|
||||
|
||||
is_enabled = ret & (CHAN_MASK(chan0) | CHAN_MASK(chan1));
|
||||
|
||||
if (is_enabled)
|
||||
admin_state->c33_admin_state =
|
||||
ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED;
|
||||
else
|
||||
admin_state->c33_admin_state =
|
||||
ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int si3474_pi_get_pw_status(struct pse_controller_dev *pcdev, int id,
|
||||
struct pse_pw_status *pw_status)
|
||||
{
|
||||
struct si3474_priv *priv = to_si3474_priv(pcdev);
|
||||
struct i2c_client *client;
|
||||
bool delivering;
|
||||
u8 chan0, chan1;
|
||||
s32 ret;
|
||||
|
||||
si3474_get_channels(priv, id, &chan0, &chan1);
|
||||
client = si3474_get_chan_client(priv, chan0);
|
||||
|
||||
ret = i2c_smbus_read_byte_data(client, POWER_STATUS_REG);
|
||||
if (ret < 0) {
|
||||
pw_status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN;
|
||||
return ret;
|
||||
}
|
||||
|
||||
delivering = ret & (CHAN_UPPER_BIT(chan0) | CHAN_UPPER_BIT(chan1));
|
||||
|
||||
if (delivering)
|
||||
pw_status->c33_pw_status =
|
||||
ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING;
|
||||
else
|
||||
pw_status->c33_pw_status = ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int si3474_get_of_channels(struct si3474_priv *priv)
|
||||
{
|
||||
struct pse_pi *pi;
|
||||
u32 chan_id;
|
||||
u8 pi_no;
|
||||
s32 ret;
|
||||
|
||||
for (pi_no = 0; pi_no < SI3474_MAX_CHANS; pi_no++) {
|
||||
pi = &priv->pcdev.pi[pi_no];
|
||||
bool pairset_found = false;
|
||||
u8 pairset_no;
|
||||
|
||||
for (pairset_no = 0; pairset_no < 2; pairset_no++) {
|
||||
if (!pi->pairset[pairset_no].np)
|
||||
continue;
|
||||
|
||||
pairset_found = true;
|
||||
|
||||
ret = of_property_read_u32(pi->pairset[pairset_no].np,
|
||||
"reg", &chan_id);
|
||||
if (ret) {
|
||||
dev_err(&priv->client[0]->dev,
|
||||
"Failed to read channel reg property\n");
|
||||
return ret;
|
||||
}
|
||||
if (chan_id > SI3474_MAX_CHANS) {
|
||||
dev_err(&priv->client[0]->dev,
|
||||
"Incorrect channel number: %d\n", chan_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
priv->pi[pi_no].chan[pairset_no] = chan_id;
|
||||
/* Mark as 4-pair if second pairset is present */
|
||||
priv->pi[pi_no].is_4p = (pairset_no == 1);
|
||||
}
|
||||
|
||||
if (pairset_found && !priv->pi[pi_no].is_4p) {
|
||||
dev_err(&priv->client[0]->dev,
|
||||
"Second pairset is missing for PI %pOF, only 4p configs are supported\n",
|
||||
pi->np);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int si3474_setup_pi_matrix(struct pse_controller_dev *pcdev)
|
||||
{
|
||||
struct si3474_priv *priv = to_si3474_priv(pcdev);
|
||||
s32 ret;
|
||||
|
||||
ret = si3474_get_of_channels(priv);
|
||||
if (ret < 0)
|
||||
dev_warn(&priv->client[0]->dev,
|
||||
"Unable to parse DT PSE power interface matrix\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int si3474_pi_enable(struct pse_controller_dev *pcdev, int id)
|
||||
{
|
||||
struct si3474_priv *priv = to_si3474_priv(pcdev);
|
||||
struct i2c_client *client;
|
||||
u8 chan0, chan1;
|
||||
s32 ret;
|
||||
u8 val;
|
||||
|
||||
si3474_get_channels(priv, id, &chan0, &chan1);
|
||||
client = si3474_get_chan_client(priv, chan0);
|
||||
|
||||
/* Release PI from shutdown */
|
||||
ret = i2c_smbus_read_byte_data(client, PORT_MODE_REG);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
val = (u8)ret;
|
||||
val |= CHAN_MASK(chan0);
|
||||
val |= CHAN_MASK(chan1);
|
||||
|
||||
ret = i2c_smbus_write_byte_data(client, PORT_MODE_REG, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* DETECT_CLASS_ENABLE must be set when using AUTO mode,
|
||||
* otherwise PI does not power up - datasheet section 2.10.2
|
||||
*/
|
||||
val = CHAN_BIT(chan0) | CHAN_UPPER_BIT(chan0) |
|
||||
CHAN_BIT(chan1) | CHAN_UPPER_BIT(chan1);
|
||||
|
||||
ret = i2c_smbus_write_byte_data(client, DETECT_CLASS_ENABLE_REG, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int si3474_pi_disable(struct pse_controller_dev *pcdev, int id)
|
||||
{
|
||||
struct si3474_priv *priv = to_si3474_priv(pcdev);
|
||||
struct i2c_client *client;
|
||||
u8 chan0, chan1;
|
||||
s32 ret;
|
||||
u8 val;
|
||||
|
||||
si3474_get_channels(priv, id, &chan0, &chan1);
|
||||
client = si3474_get_chan_client(priv, chan0);
|
||||
|
||||
/* Set PI in shutdown mode */
|
||||
ret = i2c_smbus_read_byte_data(client, PORT_MODE_REG);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
val = (u8)ret;
|
||||
val &= ~CHAN_MASK(chan0);
|
||||
val &= ~CHAN_MASK(chan1);
|
||||
|
||||
ret = i2c_smbus_write_byte_data(client, PORT_MODE_REG, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int si3474_pi_get_chan_current(struct si3474_priv *priv, u8 chan)
|
||||
{
|
||||
struct i2c_client *client;
|
||||
u64 tmp_64;
|
||||
s32 ret;
|
||||
u8 reg;
|
||||
|
||||
client = si3474_get_chan_client(priv, chan);
|
||||
|
||||
/* Registers 0x30 to 0x3d */
|
||||
reg = CHAN_REG(PORT1_CURRENT_LSB_REG, chan);
|
||||
|
||||
ret = i2c_smbus_read_word_data(client, reg);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
tmp_64 = ret * SI3474_NA_STEP;
|
||||
|
||||
/* uA = nA / 1000 */
|
||||
tmp_64 = DIV_ROUND_CLOSEST_ULL(tmp_64, 1000);
|
||||
return (int)tmp_64;
|
||||
}
|
||||
|
||||
static int si3474_pi_get_chan_voltage(struct si3474_priv *priv, u8 chan)
|
||||
{
|
||||
struct i2c_client *client;
|
||||
s32 ret;
|
||||
u32 val;
|
||||
u8 reg;
|
||||
|
||||
client = si3474_get_chan_client(priv, chan);
|
||||
|
||||
/* Registers 0x32 to 0x3f */
|
||||
reg = CHAN_REG(PORT1_VOLTAGE_LSB_REG, chan);
|
||||
|
||||
ret = i2c_smbus_read_word_data(client, reg);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
val = ret * SI3474_UV_STEP;
|
||||
|
||||
return (int)val;
|
||||
}
|
||||
|
||||
static int si3474_pi_get_voltage(struct pse_controller_dev *pcdev, int id)
|
||||
{
|
||||
struct si3474_priv *priv = to_si3474_priv(pcdev);
|
||||
struct i2c_client *client;
|
||||
u8 chan0, chan1;
|
||||
s32 ret;
|
||||
|
||||
si3474_get_channels(priv, id, &chan0, &chan1);
|
||||
client = si3474_get_chan_client(priv, chan0);
|
||||
|
||||
/* Check which channels are enabled*/
|
||||
ret = i2c_smbus_read_byte_data(client, POWER_STATUS_REG);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Take voltage from the first enabled channel */
|
||||
if (ret & CHAN_BIT(chan0))
|
||||
ret = si3474_pi_get_chan_voltage(priv, chan0);
|
||||
else if (ret & CHAN_BIT(chan1))
|
||||
ret = si3474_pi_get_chan_voltage(priv, chan1);
|
||||
else
|
||||
/* 'should' be no voltage in this case */
|
||||
return 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int si3474_pi_get_actual_pw(struct pse_controller_dev *pcdev, int id)
|
||||
{
|
||||
struct si3474_priv *priv = to_si3474_priv(pcdev);
|
||||
u8 chan0, chan1;
|
||||
u32 uV, uA;
|
||||
u64 tmp_64;
|
||||
s32 ret;
|
||||
|
||||
ret = si3474_pi_get_voltage(&priv->pcdev, id);
|
||||
|
||||
/* Do not read currents if voltage is 0 */
|
||||
if (ret <= 0)
|
||||
return ret;
|
||||
uV = ret;
|
||||
|
||||
si3474_get_channels(priv, id, &chan0, &chan1);
|
||||
|
||||
ret = si3474_pi_get_chan_current(priv, chan0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
uA = ret;
|
||||
|
||||
ret = si3474_pi_get_chan_current(priv, chan1);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
uA += ret;
|
||||
|
||||
tmp_64 = uV;
|
||||
tmp_64 *= uA;
|
||||
/* mW = uV * uA / 1000000000 */
|
||||
return DIV_ROUND_CLOSEST_ULL(tmp_64, 1000000000);
|
||||
}
|
||||
|
||||
static const struct pse_controller_ops si3474_ops = {
|
||||
.setup_pi_matrix = si3474_setup_pi_matrix,
|
||||
.pi_enable = si3474_pi_enable,
|
||||
.pi_disable = si3474_pi_disable,
|
||||
.pi_get_actual_pw = si3474_pi_get_actual_pw,
|
||||
.pi_get_voltage = si3474_pi_get_voltage,
|
||||
.pi_get_admin_state = si3474_pi_get_admin_state,
|
||||
.pi_get_pw_status = si3474_pi_get_pw_status,
|
||||
};
|
||||
|
||||
static void si3474_ancillary_i2c_remove(void *data)
|
||||
{
|
||||
struct i2c_client *client = data;
|
||||
|
||||
i2c_unregister_device(client);
|
||||
}
|
||||
|
||||
static int si3474_i2c_probe(struct i2c_client *client)
|
||||
{
|
||||
struct device *dev = &client->dev;
|
||||
struct si3474_priv *priv;
|
||||
u8 fw_version;
|
||||
s32 ret;
|
||||
|
||||
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
|
||||
dev_err(dev, "i2c check functionality failed\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = i2c_smbus_read_byte_data(client, VENDOR_IC_ID_REG);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (ret != SI3474_DEVICE_ID) {
|
||||
dev_err(dev, "Wrong device ID: 0x%x\n", ret);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
ret = i2c_smbus_read_byte_data(client, FIRMWARE_REVISION_REG);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
fw_version = ret;
|
||||
|
||||
ret = i2c_smbus_read_byte_data(client, CHIP_REVISION_REG);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
dev_dbg(dev, "Chip revision: 0x%x, firmware version: 0x%x\n",
|
||||
ret, fw_version);
|
||||
|
||||
priv->client[0] = client;
|
||||
i2c_set_clientdata(client, priv);
|
||||
|
||||
priv->client[1] = i2c_new_ancillary_device(priv->client[0], "secondary",
|
||||
priv->client[0]->addr + 1);
|
||||
if (IS_ERR(priv->client[1]))
|
||||
return PTR_ERR(priv->client[1]);
|
||||
|
||||
ret = devm_add_action_or_reset(dev, si3474_ancillary_i2c_remove, priv->client[1]);
|
||||
if (ret < 0) {
|
||||
dev_err(&priv->client[1]->dev, "Cannot register remove callback\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = i2c_smbus_read_byte_data(priv->client[1], VENDOR_IC_ID_REG);
|
||||
if (ret < 0) {
|
||||
dev_err(&priv->client[1]->dev, "Cannot access secondary PSE controller\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (ret != SI3474_DEVICE_ID) {
|
||||
dev_err(&priv->client[1]->dev,
|
||||
"Wrong device ID for secondary PSE controller: 0x%x\n", ret);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
priv->np = dev->of_node;
|
||||
priv->pcdev.owner = THIS_MODULE;
|
||||
priv->pcdev.ops = &si3474_ops;
|
||||
priv->pcdev.dev = dev;
|
||||
priv->pcdev.types = ETHTOOL_PSE_C33;
|
||||
priv->pcdev.nr_lines = SI3474_MAX_CHANS;
|
||||
|
||||
ret = devm_pse_controller_register(dev, &priv->pcdev);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to register PSE controller: 0x%x\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id si3474_id[] = {
|
||||
{ "si3474" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, si3474_id);
|
||||
|
||||
static const struct of_device_id si3474_of_match[] = {
|
||||
{
|
||||
.compatible = "skyworks,si3474",
|
||||
},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, si3474_of_match);
|
||||
|
||||
static struct i2c_driver si3474_driver = {
|
||||
.probe = si3474_i2c_probe,
|
||||
.id_table = si3474_id,
|
||||
.driver = {
|
||||
.name = "si3474",
|
||||
.of_match_table = si3474_of_match,
|
||||
},
|
||||
};
|
||||
module_i2c_driver(si3474_driver);
|
||||
|
||||
MODULE_AUTHOR("Piotr Kubik <piotr.kubik@adtran.com>");
|
||||
MODULE_DESCRIPTION("Skyworks Si3474 PoE PSE Controller driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user