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rk3228: initialize platform data
Change-Id: Id7fd0d98ef70641a62bd8520b72214141b5cf199 Signed-off-by: Chen Liang <cl@rock-chips.com>
This commit is contained in:
Chen Liang
Gerrit Code Review
parent
6631b869a9
commit
8446bec195
2162
arch/arm/boot/dts/rk3228-clocks.dtsi
Normal file
2162
arch/arm/boot/dts/rk3228-clocks.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
153
arch/arm/boot/dts/rk3228-fpga.dts
Normal file
153
arch/arm/boot/dts/rk3228-fpga.dts
Normal file
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@ -0,0 +1,153 @@
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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#include "rk3228-clocks.dtsi"
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/ {
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compatible = "rockchip,rk3228";
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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};
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};
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gic: interrupt-controller@32010000 {
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compatible = "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0x32011000 0x1000>,
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<0x32012000 0x1000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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memory {
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device_type = "memory";
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reg = <0x60000000 0x10000000>;
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};
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chosen {
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bootargs = "initrd=0x62000000,0x00180000 init=/init console=ttyFIQ0,115200 earlyprintk=uart8250-32bit,0x11030000";
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};
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aliases {
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serial2 = &uart_dbg;
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};
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uart_dbg: serial@11030000 {
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compatible = "rockchip,serial";
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reg = <0x11030000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&xin24m>, <&xin24m>;
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clock-names = "sclk_uart", "pclk_uart";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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rockchip,serial-id = <2>;
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rockchip,signal-irq = <159>;
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rockchip,wake-irq = <0>;
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rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
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rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
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//status = "disabled";
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};
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rockchip_clocks_init: clocks-init{
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compatible = "rockchip,clocks-init";
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rockchip,clocks-init-parent =
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<&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
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<&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
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<&aclk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
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<&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
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<&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
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<&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
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<&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>;
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rockchip,clocks-init-rate =
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<&clk_gpll 600000000>, <&clk_core 700000000>,
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<&clk_cpll 500000000>, <&aclk_bus 250000000>,
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<&hclk_bus 125000000>, <&pclk_bus 62500000>,
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<&aclk_peri 250000000>, <&hclk_peri 125000000>,
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<&pclk_peri 62500000>, <&clk_mac 125000000>,
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<&aclk_iep 250000000>, <&hclk_vio 125000000>,
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<&aclk_rga 250000000>, <&aclk_gpu 250000000>,
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<&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
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<&clk_vdec_cabac 250000000>;
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/*
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rockchip,clocks-uboot-has-init =
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<&aclk_vio0>;
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*/
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};
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rockchip_clocks_enable: clocks-enable {
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compatible = "rockchip,clocks-enable";
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clocks =
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/*PLL*/
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<&clk_apll>,
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<&clk_dpll>,
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<&clk_gpll>,
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<&clk_cpll>,
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/*PD_CORE*/
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<&clk_core>,
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<&pclk_dbg>,
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<&aclk_core>,
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<&clk_gates4 2>,
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/*PD_BUS*/
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<&aclk_bus>,
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<&hclk_bus>,
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<&pclk_bus>,
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<&clk_gates8 0>,/*aclk_intmem*/
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<&clk_gates8 1>,/*clk_intmem_mbist*/
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<&clk_gates8 3>,/*aclk_dmac_bus*/
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<&clk_gates10 1>,/*g_aclk_bus*/
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<&clk_gates13 9>,/*aclk_gic400*/
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<&clk_gates8 3>,/*hclk_rom*/
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<&clk_gates8 4>,/*pclk_ddrupctl*/
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<&clk_gates8 6>,/*pclk_ddrmon*/
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<&clk_gates9 4>,/*pclk_timer0*/
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<&clk_gates9 5>,/*pclk_stimer*/
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<&clk_gates10 0>,/*pclk_grf*/
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<&clk_gates10 4>,/*pclk_cru*/
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<&clk_gates10 6>,/*pclk_sgrf*/
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<&clk_gates10 3>,/*pclk_ddrphy*/
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<&clk_gates10 9>,/*pclk_phy_noc*/
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/*PD_PERI*/
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<&aclk_peri>,
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<&hclk_peri>,
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<&pclk_peri>,
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<&clk_gates12 0>,/*aclk_peri_noc*/
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<&clk_gates12 1>,/*hclk_peri_noc*/
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<&clk_gates12 2>,/*pclk_peri_noc*/
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<&clk_gates6 5>, /* g_clk_timer0 */
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<&clk_gates6 6>, /* g_clk_timer1 */
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<&clk_gates7 14>, /* g_aclk_gpu */
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<&clk_gates7 15>, /* g_aclk_gpu_noc */
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<&clk_gates1 3>;/*clk_jtag*/
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};
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};
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@ -5,6 +5,7 @@ obj-y += rk312x.o
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obj-y += rk3126b.o
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obj-y += rk3188.o
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obj-y += rk3288.o
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obj-y += rk3228.o
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ifneq ($(CONFIG_ARM_TRUSTZONE),y)
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obj-y += ddr_freq.o
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endif
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115
arch/arm/mach-rockchip/rk3228.c
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115
arch/arm/mach-rockchip/rk3228.c
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@ -0,0 +1,115 @@
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/*
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* Copyright (C) 2015 ROCKCHIP, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clocksource.h>
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#include <linux/cpuidle.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/irqchip.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/rockchip/common.h>
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#include <linux/rockchip/cpu.h>
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#include <linux/rockchip/cpu_axi.h>
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#include <linux/rockchip/cru.h>
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#include <linux/rockchip/dvfs.h>
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#include <linux/rockchip/grf.h>
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#include <linux/rockchip/iomap.h>
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#include <linux/rockchip/pmu.h>
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#include <asm/cputype.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "loader.h"
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#define CPU 3228
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#include "sram.h"
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#include <linux/rockchip/cpu.h>
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#define RK3228_DEVICE(name) \
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{ \
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.virtual = (unsigned long) RK_##name##_VIRT, \
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.pfn = __phys_to_pfn(RK3228_##name##_PHYS), \
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.length = RK3228_##name##_SIZE, \
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.type = MT_DEVICE, \
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}
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static const char * const rk3228_dt_compat[] __initconst = {
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"rockchip,rk3228",
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NULL,
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};
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static struct map_desc rk3228_io_desc[] __initdata = {
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RK3228_DEVICE(CRU),
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RK3228_DEVICE(GRF),
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RK3228_DEVICE(TIMER),
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RK3228_DEVICE(CPU_AXI_BUS),
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RK_DEVICE(RK_DEBUG_UART_VIRT, RK3228_UART2_PHYS, RK3228_UART_SIZE),
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RK_DEVICE(RK_DDR_VIRT, RK3228_DDR_PCTL_PHYS, RK3228_DDR_PCTL_SIZE),
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RK_DEVICE(RK_DDR_VIRT + RK3228_DDR_PCTL_SIZE, RK3228_DDR_PHY_PHYS,
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RK3228_DDR_PHY_SIZE),
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RK_DEVICE(RK_GPIO_VIRT(0), RK3228_GPIO0_PHYS, RK3228_GPIO_SIZE),
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RK_DEVICE(RK_GPIO_VIRT(1), RK3228_GPIO1_PHYS, RK3228_GPIO_SIZE),
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RK_DEVICE(RK_GPIO_VIRT(2), RK3228_GPIO2_PHYS, RK3228_GPIO_SIZE),
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RK_DEVICE(RK_GPIO_VIRT(3), RK3228_GPIO3_PHYS, RK3228_GPIO_SIZE),
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RK_DEVICE(RK_GIC_VIRT, RK3228_GIC_DIST_PHYS, RK3228_GIC_DIST_SIZE),
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RK_DEVICE(RK_GIC_VIRT + RK3228_GIC_DIST_SIZE, RK3228_GIC_CPU_PHYS,
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RK3228_GIC_CPU_SIZE),
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RK_DEVICE(RK_PWM_VIRT, RK3228_PWM_PHYS, RK3228_PWM_SIZE),
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};
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void __init rk3228_dt_map_io(void)
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{
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rockchip_soc_id = ROCKCHIP_SOC_RK3228;
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iotable_init(rk3228_io_desc, ARRAY_SIZE(rk3228_io_desc));
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debug_ll_io_init();
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}
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static void __init rk3228_dt_init_timer(void)
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{
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of_clk_init(NULL);
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clocksource_of_init();
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of_dvfs_init();
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}
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static void __init rk3228_reserve(void)
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{
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/* reserve memory for uboot */
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rockchip_uboot_mem_reserve();
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/* reserve memory for ION */
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rockchip_ion_reserve();
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}
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static void __init rk3228_init_late(void)
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{
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if (rockchip_jtag_enabled)
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clk_prepare_enable(clk_get_sys(NULL, "clk_jtag"));
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}
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static void rk3228_restart(char mode, const char *cmd)
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{
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}
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DT_MACHINE_START(RK3228_DT, "Rockchip RK3228")
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.smp = smp_ops(rockchip_smp_ops),
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.map_io = rk3228_dt_map_io,
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.init_time = rk3228_dt_init_timer,
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.dt_compat = rk3228_dt_compat,
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.init_late = rk3228_init_late,
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.reserve = rk3228_reserve,
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.restart = rk3228_restart,
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MACHINE_END
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@ -232,9 +232,10 @@ static const struct pll_clk_set rk3036plus_pll_com_table[] = {
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static const struct pll_clk_set rk312xplus_pll_com_table[] = {
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/*_RK3036_PLL_SET_CLKS(1064000, 3, 133, 1, 1, 1, 0),*/
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/*_RK3036_PLL_SET_CLKS(798000, 2, 133, 2, 1, 1, 0),*/
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_RK3036_PLL_SET_CLKS(1000000, 3, 125, 1, 1, 1, 0),
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_RK3036_PLL_SET_CLKS(594000, 2, 99, 2, 1, 1, 0),
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_RK3036_PLL_SET_CLKS(500000, 6, 250, 2, 1, 1, 0),
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_RK3036_PLL_SET_CLKS(400000, 6, 400, 2, 2, 1, 0),
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_RK3036_PLL_SET_CLKS(500000, 3, 125, 2, 1, 1, 0),
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_RK3036_PLL_SET_CLKS(400000, 3, 200, 2, 2, 1, 0),
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};
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static const struct apll_clk_set rk3368_apllb_table[] = {
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@ -1960,7 +1961,7 @@ static int clk_pll_set_rate_3036_apll(struct clk_hw *hw, unsigned long rate,
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/************select apll******************/
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cru_writel(RK3036_CORE_SEL_PLL(0), RK3036_CRU_CLKSELS_CON(0));
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/**************return slow mode***********/
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/*cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);*/
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cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
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cru_writel(RK3036_CLK_CORE_DIV(1), RK3036_CRU_CLKSELS_CON(0));
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@ -2054,7 +2055,7 @@ static int clk_cpll_set_rate_312xplus(struct clk_hw *hw, unsigned long rate,
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}
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if (clk_set->rate == rate) {
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clk_debug("cpll get a rate\n");
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clk_debug("cpll get a rate %ld\n", rate);
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rk3036_pll_clk_set_rate(clk_set, hw);
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} else {
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167
include/dt-bindings/clock/rockchip,rk3228.h
Normal file
167
include/dt-bindings/clock/rockchip,rk3228.h
Normal file
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@ -0,0 +1,167 @@
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#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_RK3228_H
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#define _DT_BINDINGS_CLOCK_ROCKCHIP_RK3228_H
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#include "rockchip.h"
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/* pll id */
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#define RK3228_APLL_ID 0
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#define RK3228_DPLL_ID 1
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#define RK3228_CPLL_ID 2
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#define RK3228_GPLL_ID 3
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#define RK3228_END_PLL_ID 4
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/* reset id */
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#define RK3228_RST_CORE0_PO 0
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#define RK3228_RST_CORE1_PO 1
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#define RK3228_RST_CORE2_PO 2
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#define RK3228_RST_CORE3_PO 3
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#define RK3228_RST_CORE0 4
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#define RK3228_RST_CORE1 5
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#define RK3228_RST_CORE2 6
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#define RK3228_RST_CORE3 7
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#define RK3228_RST_CORE0_DBG 8
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#define RK3228_RST_CORE1_DBG 9
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#define RK3228_RST_CORE2_DBG 10
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#define RK3228_RST_CORE3_DBG 11
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#define RK3228_RST_TOPDBG 12
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#define RK3228_RST_ACLK_CORE 13
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#define RK3228_RST_NOC_A 14
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#define RK3228_RST_L2C 15
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#define RK3228_RST_1RES0 16
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#define RK3228_RST_1RES1 17
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#define RK3228_RST_CPUSYS_H 18
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#define RK3228_RST_BUSSYS_H 19
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#define RK3228_RST_SPDIF 20
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#define RK3228_RST_INTMEM 21
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#define RK3228_RST_ROM 22
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#define RK3228_RST_OTG_ADP 23
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#define RK3228_RST_I2S0 24
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#define RK3228_RST_I2S1 25
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#define RK3228_RST_I2S2 26
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#define RK3228_RST_ACODEC_P 27
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#define RK3228_RST_DFIMON 28
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#define RK3228_RST_MSCH 29
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#define RK3228_RST_EFUSE_1024 30
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#define RK3228_RST_EFUSE_256 31
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#define RK3228_RST_GPIO0 32
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#define RK3228_RST_GPIO1 33
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#define RK3228_RST_GPIO2 34
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#define RK3228_RST_GPIO3 35
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#define RK3228_RST_PERIPH_NOC_A 36
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#define RK3228_RST_PERIPH_NOC_H 37
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#define RK3228_RST_PERIPH_NOC_P 38
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#define RK3228_RST_UART0 39
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#define RK3228_RST_UART1 40
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#define RK3228_RST_UART2 41
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#define RK3228_RST_PHYNOC 42
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#define RK3228_RST_I2C0 43
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#define RK3228_RST_I2C1 44
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#define RK3228_RST_I2C2 45
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#define RK3228_RST_I2C3 46
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#define RK3228_RST_2RES15 47
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#define RK3228_RST_PWM0 48
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#define RK3228_RST_A53_GIC 49
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#define RK3228_RST_3RES2 50
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#define RK3228_RST_DAP 51
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#define RK3228_RST_DAP_NOC 52
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#define RK3228_RST_CRYPTO 53
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||||
#define RK3228_RST_SGRF 54
|
||||
#define RK3228_RST_GRF 55
|
||||
#define RK3228_RST_GMAC 56
|
||||
#define RK3228_RST_3RES9 57
|
||||
#define RK3228_RST_PERIPHSYS_A 58
|
||||
#define RK3228_RST_3RES11 59
|
||||
#define RK3228_RST_3RES12 60
|
||||
#define RK3228_RST_3RES13 61
|
||||
#define RK3228_RST_3RES14 62
|
||||
#define RK3228_RST_MACPHY 63
|
||||
|
||||
#define RK3228_RST_4RES0 64
|
||||
#define RK3228_RST_4RES1 65
|
||||
#define RK3228_RST_4RES2 66
|
||||
#define RK3228_RST_4RES3 67
|
||||
#define RK3228_RST_NANDC 68
|
||||
#define RK3228_RST_USBOTG0 69
|
||||
#define RK3228_RST_OTGC0 70
|
||||
#define RK3228_RST_USBHOST0 71
|
||||
#define RK3228_RST_HOST_CTRL0 72
|
||||
#define RK3228_RST_USBHOST1 73
|
||||
#define RK3228_RST_HOST_CTRL1 74
|
||||
#define RK3228_RST_USBHOST2 75
|
||||
#define RK3228_RST_HOST_CTRL2 76
|
||||
#define RK3228_RST_USBPOR0 77
|
||||
#define RK3228_RST_USBPOR1 78
|
||||
#define RK3228_RST_DDRMSCH 79
|
||||
|
||||
#define RK3228_RST_SMART_CARD 80
|
||||
#define RK3228_RST_SDMMC0 81
|
||||
#define RK3228_RST_SDIO 82
|
||||
#define RK3228_RST_EMMC 83
|
||||
#define RK3228_RST_SPI0 84
|
||||
#define RK3228_RST_TSP_H 85
|
||||
#define RK3228_RST_TSP 86
|
||||
#define RK3228_RST_TSADC 87
|
||||
#define RK3228_RST_DDRPHY 88
|
||||
#define RK3228_RST_DDRPHY_P 89
|
||||
#define RK3228_RST_DDRCTRL 90
|
||||
#define RK3228_RST_DDRCTRL_P 91
|
||||
#define RK3228_RST_HOST0_ECHI 92
|
||||
#define RK3228_RST_HOST1_ECHI 93
|
||||
#define RK3228_RST_HOST2_ECHI 94
|
||||
#define RK3228_RST_VOP 95
|
||||
|
||||
#define RK3228_RST_HDMI_P 96
|
||||
#define RK3228_RST_VIO_ARBI_H 97
|
||||
#define RK3228_RST_IEP_NOC_A 98
|
||||
#define RK3228_RST_VIO_NOC_H 99
|
||||
#define RK3228_RST_VOP_A 100
|
||||
#define RK3228_RST_VOP_H 101
|
||||
#define RK3228_RST_VOP_D 102
|
||||
#define RK3228_RST_UTMI0 103
|
||||
#define RK3228_RST_UTMI1 104
|
||||
#define RK3228_RST_UTMI2 105
|
||||
#define RK3228_RST_UTMI3 106
|
||||
#define RK3228_RST_RGA 107
|
||||
#define RK3228_RST_RGA_NOC_A 108
|
||||
#define RK3228_RST_RGA_A 109
|
||||
#define RK3228_RST_RGA_H 110
|
||||
#define RK3228_RST_HDCP_A 111
|
||||
|
||||
#define RK3228_RST_VPU_A 112
|
||||
#define RK3228_RST_VPU_H 113
|
||||
#define RK3228_RST_7RES2 114
|
||||
#define RK3228_RST_7RES3 115
|
||||
#define RK3228_RST_VPU_NOC_A 116
|
||||
#define RK3228_RST_VPU_NOC_H 117
|
||||
#define RK3228_RST_RKVDEC_A 118
|
||||
#define RK3228_RST_RKVDEC_NOC_A 119
|
||||
#define RK3228_RST_RKVDEC_H 120
|
||||
#define RK3228_RST_RKVDEC_NOC_H 121
|
||||
#define RK3228_RST_RKVDEC_CORE 122
|
||||
#define RK3228_RST_RKVDEC_CABAC 123
|
||||
#define RK3228_RST_IEP_A 124
|
||||
#define RK3228_RST_IEP_H 125
|
||||
#define RK3228_RST_GPU_A 126
|
||||
#define RK3228_RST_GPU_NOC_A 127
|
||||
|
||||
#define RK3228_RST_CORE_DBG 128
|
||||
#define RK3228_RST_DBG_P 129
|
||||
#define RK3228_RST_TIMER0 130
|
||||
#define RK3228_RST_TIMER1 131
|
||||
#define RK3228_RST_TIMER2 132
|
||||
#define RK3228_RST_TIMER3 133
|
||||
#define RK3228_RST_TIMER4 134
|
||||
#define RK3228_RST_TIMER5 135
|
||||
#define RK3228_RST_VIO_H2P 136
|
||||
#define RK3228_RST_8RES9 137
|
||||
#define RK3228_RST_8RES10 138
|
||||
#define RK3228_RST_HDMIPHY 139
|
||||
#define RK3228_RST_VDAC 140
|
||||
#define RK3228_RST_TIMER_6CH 141
|
||||
#define RK3228_RST_8RES14 142
|
||||
#define RK3228_RST_8RES15 143
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3228_H */
|
||||
|
|
@ -34,6 +34,7 @@ static inline void rockchip_set_cpu_version(unsigned long ver)
|
|||
#define ROCKCHIP_CPU_RK3188 0x31880000
|
||||
#define ROCKCHIP_CPU_RK319X 0x31900000
|
||||
#define ROCKCHIP_CPU_RK3288 0x32880000
|
||||
#define ROCKCHIP_CPU_RK3228 0x32280000
|
||||
|
||||
#ifdef CONFIG_ARM
|
||||
#define ROCKCHIP_CPU(id, ID) \
|
||||
|
|
@ -55,6 +56,7 @@ ROCKCHIP_CPU(312x, 312X)
|
|||
ROCKCHIP_CPU(3188, 3188)
|
||||
ROCKCHIP_CPU(319x, 319X)
|
||||
ROCKCHIP_CPU(3288, 3288)
|
||||
ROCKCHIP_CPU(3228, 3228)
|
||||
|
||||
#define ROCKCHIP_SOC_MASK (ROCKCHIP_CPU_MASK | 0xff)
|
||||
#define ROCKCHIP_SOC_RK2926 (ROCKCHIP_CPU_RK2928 | 0x00)
|
||||
|
|
@ -76,6 +78,7 @@ ROCKCHIP_CPU(3288, 3288)
|
|||
#define ROCKCHIP_SOC_RK3188PLUS (ROCKCHIP_CPU_RK3188 | 0x10)
|
||||
#define ROCKCHIP_SOC_RK3190 (ROCKCHIP_CPU_RK319X | 0x00)
|
||||
#define ROCKCHIP_SOC_RK3288 (ROCKCHIP_CPU_RK3288 | 0x00)
|
||||
#define ROCKCHIP_SOC_RK3228 (ROCKCHIP_CPU_RK3228 | 0x00)
|
||||
|
||||
#ifdef CONFIG_ARM
|
||||
#define ROCKCHIP_SOC(id, ID) \
|
||||
|
|
@ -107,5 +110,6 @@ ROCKCHIP_SOC(3188, 3188)
|
|||
ROCKCHIP_SOC(3188plus, 3188PLUS)
|
||||
ROCKCHIP_SOC(3190, 3190)
|
||||
ROCKCHIP_SOC(3288, 3288)
|
||||
ROCKCHIP_SOC(3228, 3228)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -187,4 +187,42 @@
|
|||
#define RK312X_PWM_PHYS 0x20050000
|
||||
#define RK312X_PWM_SIZE SZ_16K
|
||||
|
||||
#define RK3228_IMEM_PHYS RK3036_IMEM_PHYS
|
||||
#define RK3228_IMEM_SIZE SZ_32K
|
||||
#define RK3228_ROM_PHYS RK3036_ROM_PHYS
|
||||
#define RK3228_ROM_SIZE RK3036_ROM_SIZE
|
||||
#define RK3228_CPU_AXI_BUS_PHYS 0x31000000
|
||||
#define RK3228_CPU_AXI_BUS_SIZE SZ_32K
|
||||
#define RK3228_GIC_DIST_PHYS 0x32011000
|
||||
#define RK3228_GIC_DIST_SIZE SZ_4K
|
||||
#define RK3228_GIC_CPU_PHYS 0x32012000
|
||||
#define RK3228_GIC_CPU_SIZE SZ_4K
|
||||
#define RK3228_CRU_PHYS 0x110e0000
|
||||
#define RK3228_CRU_SIZE SZ_4K
|
||||
#define RK3228_DDR_PCTL_PHYS 0x11200000
|
||||
#define RK3228_DDR_PCTL_SIZE SZ_4K
|
||||
#define RK3228_GRF_PHYS 0x11000000
|
||||
#define RK3228_GRF_SIZE SZ_4K
|
||||
#define RK3228_SGRF_PHYS 0x10140000
|
||||
#define RK3228_SGRF_SIZE SZ_4K
|
||||
#define RK3228_DDR_PHY_PHYS 0x12000000
|
||||
#define RK3228_DDR_PHY_SIZE SZ_4K
|
||||
#define RK3228_TIMER_PHYS 0x110c0000
|
||||
#define RK3228_TIMER_SIZE SZ_4K
|
||||
#define RK3228_STIMER_PHYS 0x110d0000
|
||||
#define RK3228_STIMER_SIZE SZ_4K
|
||||
#define RK3228_UART0_PHYS 0x11010000
|
||||
#define RK3228_UART1_PHYS 0x11020000
|
||||
#define RK3228_UART2_PHYS 0x11030000
|
||||
#define RK3228_UART_SIZE SZ_4K
|
||||
#define RK3228_GPIO0_PHYS 0x11110000
|
||||
#define RK3228_GPIO1_PHYS 0x11120000
|
||||
#define RK3228_GPIO2_PHYS 0x11130000
|
||||
#define RK3228_GPIO3_PHYS 0x11140000
|
||||
#define RK3228_GPIO_SIZE SZ_4K
|
||||
#define RK3228_EFUSE_PHYS 0x11040000
|
||||
#define RK3228_EFUSE_SIZE SZ_4K
|
||||
#define RK3228_PWM_PHYS 0x110b0000
|
||||
#define RK3228_PWM_SIZE SZ_16K
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user