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ARM: dts: r9a06g032: Add CAN{0,1} nodes

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Add CAN{0,1} nodes to R9A06G032 (RZ/N1) SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220830164518.1381632-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2022-08-30 17:45:17 +01:00 committed by Geert Uytterhoeven
parent e357955558
commit 8419e21aff
1 changed files with 20 additions and 0 deletions
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20
arch/arm/boot/dts/r9a06g032.dtsi
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@ -423,6 +423,26 @@ gic: interrupt-controller@44101000 {
interrupts =
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
can0: can@52104000 {
compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000";
reg = <0x52104000 0x800>;
reg-io-width = <4>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
power-domains = <&sysctrl>;
status = "disabled";
};
can1: can@52105000 {
compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
reg = <0x52105000 0x800>;
reg-io-width = <4>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
power-domains = <&sysctrl>;
status = "disabled";
};
};
timer {