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drm/ast: Partially implement POST without ast device instance

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We'll have to do some of the GPU POSTing for detecting the ast device
type. Make this work without an instance of the ast device.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231116100240.22975-8-tzimmermann@suse.de
This commit is contained in:
Thomas Zimmermann 2023-11-16 10:59:26 +01:00
parent 66f843d670
commit 83ab91faf2
3 changed files with 48 additions and 31 deletions
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2
drivers/gpu/drm/ast/ast_drv.h
View File

@ -482,7 +482,7 @@ int ast_mm_init(struct ast_device *ast);
void ast_post_gpu(struct drm_device *dev);
u32 ast_mindwm(struct ast_device *ast, u32 r);
void ast_moutdwm(struct ast_device *ast, u32 r, u32 v);
void ast_patch_ahb_2500(struct ast_device *ast);
void ast_patch_ahb_2500(void __iomem *regs);
/* ast dp501 */
void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);

2
drivers/gpu/drm/ast/ast_main.c
View File

@ -113,7 +113,7 @@ static int ast_device_config_init(struct ast_device *ast)
/* Patch AST2500/AST2510 */
if ((pdev->revision & 0xf0) == 0x40) {
if (!(jregd0 & AST_VRAM_INIT_STATUS_MASK))
ast_patch_ahb_2500(ast);
ast_patch_ahb_2500(ast->regs);
}
/* Double check that it's actually working */

75
drivers/gpu/drm/ast/ast_post.c
View File

@ -77,28 +77,42 @@ ast_set_def_ext_reg(struct drm_device *dev)
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
}
u32 ast_mindwm(struct ast_device *ast, u32 r)
static u32 __ast_mindwm(void __iomem *regs, u32 r)
{
uint32_t data;
u32 data;
ast_write32(ast, 0xf004, r & 0xffff0000);
ast_write32(ast, 0xf000, 0x1);
__ast_write32(regs, 0xf004, r & 0xffff0000);
__ast_write32(regs, 0xf000, 0x1);
do {
data = ast_read32(ast, 0xf004) & 0xffff0000;
data = __ast_read32(regs, 0xf004) & 0xffff0000;
} while (data != (r & 0xffff0000));
return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
return __ast_read32(regs, 0x10000 + (r & 0x0000ffff));
}
static void __ast_moutdwm(void __iomem *regs, u32 r, u32 v)
{
u32 data;
__ast_write32(regs, 0xf004, r & 0xffff0000);
__ast_write32(regs, 0xf000, 0x1);
do {
data = __ast_read32(regs, 0xf004) & 0xffff0000;
} while (data != (r & 0xffff0000));
__ast_write32(regs, 0x10000 + (r & 0x0000ffff), v);
}
u32 ast_mindwm(struct ast_device *ast, u32 r)
{
return __ast_mindwm(ast->regs, r);
}
void ast_moutdwm(struct ast_device *ast, u32 r, u32 v)
{
uint32_t data;
ast_write32(ast, 0xf004, r & 0xffff0000);
ast_write32(ast, 0xf000, 0x1);
do {
data = ast_read32(ast, 0xf004) & 0xffff0000;
} while (data != (r & 0xffff0000));
ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
__ast_moutdwm(ast->regs, r, v);
}
/*
@ -1987,17 +2001,18 @@ static bool ast_dram_init_2500(struct ast_device *ast)
return true;
}
void ast_patch_ahb_2500(struct ast_device *ast)
void ast_patch_ahb_2500(void __iomem *regs)
{
u32 data;
u32 data;
/* Clear bus lock condition */
ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
ast_moutdwm(ast, 0x1e600084, 0x00010000);
ast_moutdwm(ast, 0x1e600088, 0x00000000);
ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
data = ast_mindwm(ast, 0x1e6e2070);
if (data & 0x08000000) { /* check fast reset */
__ast_moutdwm(regs, 0x1e600000, 0xAEED1A03);
__ast_moutdwm(regs, 0x1e600084, 0x00010000);
__ast_moutdwm(regs, 0x1e600088, 0x00000000);
__ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8);
data = __ast_mindwm(regs, 0x1e6e2070);
if (data & 0x08000000) { /* check fast reset */
/*
* If "Fast restet" is enabled for ARM-ICE debugger,
* then WDT needs to enable, that
@ -2009,16 +2024,18 @@ void ast_patch_ahb_2500(struct ast_device *ast)
* [1]:= 1:WDT will be cleeared and disabled after timeout occurs
* [0]:= 1:WDT enable
*/
ast_moutdwm(ast, 0x1E785004, 0x00000010);
ast_moutdwm(ast, 0x1E785008, 0x00004755);
ast_moutdwm(ast, 0x1E78500c, 0x00000033);
__ast_moutdwm(regs, 0x1E785004, 0x00000010);
__ast_moutdwm(regs, 0x1E785008, 0x00004755);
__ast_moutdwm(regs, 0x1E78500c, 0x00000033);
udelay(1000);
}
do {
ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
data = ast_mindwm(ast, 0x1e6e2000);
} while (data != 1);
ast_moutdwm(ast, 0x1e6e207c, 0x08000000); /* clear fast reset */
__ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8);
data = __ast_mindwm(regs, 0x1e6e2000);
} while (data != 1);
__ast_moutdwm(regs, 0x1e6e207c, 0x08000000); /* clear fast reset */
}
void ast_post_chip_2500(struct drm_device *dev)
@ -2030,7 +2047,7 @@ void ast_post_chip_2500(struct drm_device *dev)
reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
if ((reg & AST_VRAM_INIT_STATUS_MASK) == 0) {/* vga only */
/* Clear bus lock condition */
ast_patch_ahb_2500(ast);
ast_patch_ahb_2500(ast->regs);
/* Disable watchdog */
ast_moutdwm(ast, 0x1E78502C, 0x00000000);