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drm/nouveau/mmu: bump up the maximum page table depth

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GH100/GBxxx have 6-level page tables.

Signed-off-by: Ben Skeggs <bskeggs@nvidia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timur Tabi <ttabi@nvidia.com>
Tested-by: Timur Tabi <ttabi@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Ben Skeggs 2025-02-13 07:42:28 +10:00 committed by Dave Airlie
parent 0adfd612c0
commit 82df73d8ee
2 changed files with 2 additions and 2 deletions
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2
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
View File

@ -8,7 +8,7 @@ struct nvkm_vma {
struct list_head head;
struct rb_node tree;
u64 addr;
u64 size:50;
u64 size;
bool mapref:1; /* PTs (de)referenced on (un)map (vs pre-allocated). */
bool sparse:1; /* Unmapped PDEs/PTEs will not trigger MMU faults. */
#define NVKM_VMA_PAGE_NONE 7

2
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c
View File

@ -19,7 +19,7 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#define NVKM_VMM_LEVELS_MAX 5
#define NVKM_VMM_LEVELS_MAX 6
#include "vmm.h"
#include <subdev/fb.h>