github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-01 19:13:47 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm64: dts: exynos: drop clock-frequency from CPU nodes in TM2

Browse Source 
The CPU frequencies are determined by OPP table, so drop the
'clock-frequency' property.  It is not parsed by any driver.

Link: https://lore.kernel.org/r/20221204113839.151816-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Krzysztof Kozlowski 2022-12-04 12:38:38 +01:00
parent 0f2d502c32
commit 82d865b5da
1 changed files with 0 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm64/boot/dts/exynos/exynos5433.dtsi
View File

@ -89,7 +89,6 @@ cpu0: cpu@100 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x100>;
clock-frequency = <1300000000>;
clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
clock-names = "apolloclk";
operating-points-v2 = <&cluster_a53_opp_table>;
@ -108,7 +107,6 @@ cpu1: cpu@101 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x101>;
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0x8000>;
@ -125,7 +123,6 @@ cpu2: cpu@102 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x102>;
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0x8000>;
@ -142,7 +139,6 @@ cpu3: cpu@103 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x103>;
clock-frequency = <1300000000>;
operating-points-v2 = <&cluster_a53_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0x8000>;
@ -159,7 +155,6 @@ cpu4: cpu@0 {
compatible = "arm,cortex-a57";
enable-method = "psci";
reg = <0x0>;
clock-frequency = <1900000000>;
clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
clock-names = "atlasclk";
operating-points-v2 = <&cluster_a57_opp_table>;
@ -178,7 +173,6 @@ cpu5: cpu@1 {
compatible = "arm,cortex-a57";
enable-method = "psci";
reg = <0x1>;
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0xc000>;
@ -195,7 +189,6 @@ cpu6: cpu@2 {
compatible = "arm,cortex-a57";
enable-method = "psci";
reg = <0x2>;
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0xc000>;
@ -212,7 +205,6 @@ cpu7: cpu@3 {
compatible = "arm,cortex-a57";
enable-method = "psci";
reg = <0x3>;
clock-frequency = <1900000000>;
operating-points-v2 = <&cluster_a57_opp_table>;
#cooling-cells = <2>;
i-cache-size = <0xc000>;