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drm/amd/display: disable timing sync b/w odm halves
Fix for a bug where we would try to timing sync 2 odm halves. Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1333,7 +1333,9 @@ static void program_timing_sync(
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struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
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for (i = 0; i < pipe_count; i++) {
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if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
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if (!ctx->res_ctx.pipe_ctx[i].stream
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|| ctx->res_ctx.pipe_ctx[i].top_pipe
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|| ctx->res_ctx.pipe_ctx[i].prev_odm_pipe)
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continue;
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unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
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