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drm/amd/display: scale plane global alpha to 12 bits on DCN 4.2

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[why]
On DCN 4.2 the global alpha is reported using 12 bits
(MPCC_GLOBAL_ALPHA spans bits [0:11]), whereas other ASICs such as
DCN 3.1.4 use an 8-bit field (MPCC_GLOBAL_ALPHA spans bits
[16:23]). The DRM plane alpha property is 16-bit and amdgpu_dm
unconditionally scaled it down by >> 8, which only matches the 8-bit
hardware field. On DCN 4.2 this fed a value that was 4 bits too small
into the 12-bit field, so the hardware applied the wrong global alpha
and the resulting blended output did not match the expected hw * alpha
value.

[how]
Detect DCN 4.2 via amdgpu_ip_version(adev, DCE_HWIP, 0) and scale the
16-bit plane alpha by >> 4 to fill the 12-bit MPCC_GLOBAL_ALPHA field.
All other ASICs keep the existing >> 8 behavior for their 8-bit field.

Reviewed-by: ChiaHsuan (Tom) Chung <chiahsuan.chung@amd.com>
Signed-off-by: James Lin <PingLei.Lin@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
James Lin 2026-06-16 15:33:20 +08:00 committed by Alex Deucher
parent 418755e47a
commit 829769f1cf
1 changed files with 11 additions and 1 deletions
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12
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
View File

@ -137,8 +137,18 @@ void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state
}
if (plane_state->alpha < 0xffff) {
struct amdgpu_device *adev = drm_to_adev(plane_state->plane->dev);
*global_alpha = true;
*global_alpha_value = plane_state->alpha >> 8;
/*
* DCN 4.2 uses a 12-bit MPCC_GLOBAL_ALPHA field, while
* other ASICs use an 8-bit field. The DRM plane alpha is
* 16-bit, so scale it down to the width the hardware expects.
*/
if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0))
*global_alpha_value = plane_state->alpha >> 4;
else
*global_alpha_value = plane_state->alpha >> 8;
}
}
EXPORT_IF_KUNIT(amdgpu_dm_plane_fill_blending_from_plane_state);