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drm/xe/oa: Add MMIO trigger support

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Add MMIO trigger support and allow-list required registers for MMIO trigger
use case. Registers are whitelisted for the lifetime of the driver but MMIO
trigger is enabled only for the duration of the stream.

Bspec: 45925, 60340, 61228

Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240618014609.3233427-15-ashutosh.dixit@intel.com
This commit is contained in:
Ashutosh Dixit 2024-06-17 18:46:06 -07:00
parent 392bf22238
commit 828a8eaf37
3 changed files with 51 additions and 2 deletions
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5
drivers/gpu/drm/xe/regs/xe_oa_regs.h
View File

@ -60,6 +60,10 @@
#define OA_OACONTROL_COUNTER_SIZE_MASK REG_GENMASK(8, 8)
#define OAG_OA_DEBUG XE_REG(0xdaf8, XE_REG_OPTION_MASKED)
#define OAG_OA_DEBUG_DISABLE_MMIO_TRG REG_BIT(14)
#define OAG_OA_DEBUG_START_TRIGGER_SCOPE_CONTROL REG_BIT(13)
#define OAG_OA_DEBUG_DISABLE_START_TRG_2_COUNT_QUAL REG_BIT(8)
#define OAG_OA_DEBUG_DISABLE_START_TRG_1_COUNT_QUAL REG_BIT(7)
#define OAG_OA_DEBUG_INCLUDE_CLK_RATIO REG_BIT(6)
#define OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS REG_BIT(5)
#define OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS REG_BIT(1)
@ -69,6 +73,7 @@
#define OASTATUS_COUNTER_OVERFLOW REG_BIT(2)
#define OASTATUS_BUFFER_OVERFLOW REG_BIT(1)
#define OASTATUS_REPORT_LOST REG_BIT(0)
#define OAG_MMIOTRIGGER XE_REG(0xdb1c)
/* OAC unit */
#define OAC_OACONTROL XE_REG(0x15114)

24
drivers/gpu/drm/xe/xe_oa.c
View File

@ -760,6 +760,13 @@ static int xe_oa_configure_oa_context(struct xe_oa_stream *stream, bool enable)
#define HAS_OA_BPC_REPORTING(xe) (GRAPHICS_VERx100(xe) >= 1255)
static u32 oag_configure_mmio_trigger(const struct xe_oa_stream *stream, bool enable)
{
return _MASKED_FIELD(OAG_OA_DEBUG_DISABLE_MMIO_TRG,
enable && stream && stream->sample ?
0 : OAG_OA_DEBUG_DISABLE_MMIO_TRG);
}
static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
{
u32 sqcnt1;
@ -775,6 +782,9 @@ static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
_MASKED_BIT_DISABLE(DISABLE_DOP_GATING));
}
xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_debug,
oag_configure_mmio_trigger(stream, false));
/* disable the context save/restore or OAR counters */
if (stream->exec_q)
xe_oa_configure_oa_context(stream, false);
@ -927,9 +937,17 @@ static int xe_oa_enable_metric_set(struct xe_oa_stream *stream)
oa_debug = OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
OAG_OA_DEBUG_INCLUDE_CLK_RATIO;
if (GRAPHICS_VER(stream->oa->xe) >= 20)
oa_debug |=
/* The three bits below are needed to get PEC counters running */
OAG_OA_DEBUG_START_TRIGGER_SCOPE_CONTROL |
OAG_OA_DEBUG_DISABLE_START_TRG_2_COUNT_QUAL |
OAG_OA_DEBUG_DISABLE_START_TRG_1_COUNT_QUAL;
xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_debug,
_MASKED_BIT_ENABLE(oa_debug) |
oag_report_ctx_switches(stream));
oag_report_ctx_switches(stream) |
oag_configure_mmio_trigger(stream, true));
xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_ctx_ctrl, stream->periodic ?
(OAG_OAGLBCTXCTRL_COUNTER_RESUME |
@ -2203,6 +2221,10 @@ static void __xe_oa_init_oa_units(struct xe_gt *gt)
u->type = DRM_XE_OA_UNIT_TYPE_OAM;
}
/* Ensure MMIO trigger remains disabled till there is a stream */
xe_mmio_write32(gt, u->regs.oa_debug,
oag_configure_mmio_trigger(NULL, false));
/* Set oa_unit_ids now to ensure ids remain contiguous */
u->oa_unit_id = gt_to_xe(gt)->oa.oa_unit_ids++;
}

24
drivers/gpu/drm/xe/xe_reg_whitelist.c
View File

@ -7,6 +7,7 @@
#include "regs/xe_engine_regs.h"
#include "regs/xe_gt_regs.h"
#include "regs/xe_oa_regs.h"
#include "regs/xe_regs.h"
#include "xe_gt_types.h"
#include "xe_platform_types.h"
@ -63,7 +64,28 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0))
},
{ XE_RTP_NAME("oa_reg_render"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER,
RING_FORCE_TO_NONPRIV_ACCESS_RW),
WHITELIST(OAG_OASTATUS,
RING_FORCE_TO_NONPRIV_ACCESS_RD),
WHITELIST(OAG_OAHEADPTR,
RING_FORCE_TO_NONPRIV_ACCESS_RD |
RING_FORCE_TO_NONPRIV_RANGE_4))
},
{ XE_RTP_NAME("oa_reg_compute"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
ENGINE_CLASS(COMPUTE)),
XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER,
RING_FORCE_TO_NONPRIV_ACCESS_RW),
WHITELIST(OAG_OASTATUS,
RING_FORCE_TO_NONPRIV_ACCESS_RD),
WHITELIST(OAG_OAHEADPTR,
RING_FORCE_TO_NONPRIV_ACCESS_RD |
RING_FORCE_TO_NONPRIV_RANGE_4))
},
{}
};