github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-07-28 10:09:10 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/amd/display: Add DCN42B DMUB support

Browse Source 
[Why & How]
Add DMUB support for DCN42B

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Matthew Stewart 2026-05-18 21:49:14 -04:00 committed by Alex Deucher
parent 0a5e0416e1
commit 827d94e613
5 changed files with 53 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/amd/display/dmub/dmub_srv.h
View File

@ -121,6 +121,7 @@ enum dmub_asic {
DMUB_ASIC_DCN36,
DMUB_ASIC_DCN401,
DMUB_ASIC_DCN42,
DMUB_ASIC_DCN42B,
DMUB_ASIC_MAX,
};

1
drivers/gpu/drm/amd/display/dmub/src/Makefile
View File

@ -29,6 +29,7 @@ DMUB += dmub_dcn351.o
DMUB += dmub_dcn36.o
DMUB += dmub_dcn401.o
DMUB += dmub_dcn42.o
DMUB += dmub_dcn42b.o
AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))

34
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42b.c Normal file
View File

@ -0,0 +1,34 @@
/* SPDX-License-Identifier: MIT */
/* Copyright 2026 Advanced Micro Devices, Inc. */
#include "../dmub_srv.h"
#include "dmub_reg.h"
#include "dmub_dcn42b.h"
#include "dcn/dcn_4_2_1_offset.h"
#include "dcn/dcn_4_2_1_sh_mask.h"
#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
#define CTX dmub
#define REGS dmub->regs_dcn42
#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
void dmub_srv_dcn42b_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)
{
struct dmub_srv_dcn42_regs *regs = dmub->regs_dcn42;
#define REG_STRUCT regs
#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
DMUB_DCN42_REGS()
DMCUB_INTERNAL_REGS()
#undef DMUB_SR
#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
DMUB_DCN42_FIELDS()
#undef DMUB_SF
#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
DMUB_DCN42_FIELDS()
#undef DMUB_SF
#undef REG_STRUCT
}

13
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42b.h Normal file
View File

@ -0,0 +1,13 @@
/* SPDX-License-Identifier: MIT */
/* Copyright 2026 Advanced Micro Devices, Inc. */
#ifndef _DMUB_DCN42B_H_
#define _DMUB_DCN42B_H_
#include "dmub_dcn42.h"
struct dmub_srv;
void dmub_srv_dcn42b_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);
#endif /* _DMUB_DCN42B_H_ */

4
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
View File

@ -41,6 +41,7 @@
#include "dmub_dcn36.h"
#include "dmub_dcn401.h"
#include "dmub_dcn42.h"
#include "dmub_dcn42b.h"
#include "os_types.h"
/*
* Note: the DMUB service is standalone. No additional headers should be
@ -413,6 +414,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
funcs->should_detect = dmub_dcn35_should_detect;
break;
case DMUB_ASIC_DCN42:
case DMUB_ASIC_DCN42B:
dmub->regs_dcn42 = &dmub_srv_dcn42_regs;
funcs->configure_dmub_in_system_memory = dmub_dcn42_configure_dmub_in_system_memory;
funcs->send_inbox0_cmd = dmub_dcn42_send_inbox0_cmd;
@ -466,6 +468,8 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
funcs->enable_reg_inbox0_rsp_int = dmub_dcn42_enable_reg_inbox0_rsp_int;
funcs->enable_reg_outbox0_rdy_int = dmub_dcn42_enable_reg_outbox0_rdy_int;
funcs->init_reg_offsets = dmub_srv_dcn42_regs_init;
if (asic == DMUB_ASIC_DCN42B)
funcs->init_reg_offsets = dmub_srv_dcn42b_regs_init;
funcs->is_hw_powered_up = dmub_dcn42_is_hw_powered_up;
funcs->should_detect = dmub_dcn42_should_detect;