From bd76d73836fa903d67eaabcb3a0201d2d0a73461 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 2 Mar 2015 00:12:03 +0100 Subject: [PATCH 1/3] ARM: rockchip: Constify struct regmap_config and staticize local function The regmap_config struct may be const because it is not modified by the driver and regmap_init() accepts pointer to const. Make function rockchip_get_core_reset() static because it is not used outside of the platsmp.c file. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/platsmp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index f26fcdca2445..5b4ca3c3c879 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -55,7 +55,7 @@ static int pmu_power_domain_is_on(int pd) return !(val & BIT(pd)); } -struct reset_control *rockchip_get_core_reset(int cpu) +static struct reset_control *rockchip_get_core_reset(int cpu) { struct device *dev = get_cpu_device(cpu); struct device_node *np; @@ -201,7 +201,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node) return 0; } -static struct regmap_config rockchip_pmu_regmap_config = { +static const struct regmap_config rockchip_pmu_regmap_config = { .reg_bits = 32, .val_bits = 32, .reg_stride = 4, From aefc7c7512455c26574ae7118429920dc3de60ae Mon Sep 17 00:00:00 2001 From: Chris Zhong Date: Mon, 9 Feb 2015 21:12:22 +0800 Subject: [PATCH 2/3] ARM: rockchip: decrease the wait time for resume The register-default delay time for wait the 24MHz OSC stabilization as well as PMU stabilization is 750ms, let's decrease them to a still safe 30ms. Signed-off-by: Chris Zhong Reviewed-by: Doug Anderson Tested-by: Doug Anderson Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/pm.c | 3 +++ arch/arm/mach-rockchip/pm.h | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c index 50cb781aaa36..a3ab3979923c 100644 --- a/arch/arm/mach-rockchip/pm.c +++ b/arch/arm/mach-rockchip/pm.c @@ -209,6 +209,9 @@ static int rk3288_suspend_init(struct device_node *np) memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume, rk3288_bootram_sz); + regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH); + regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH); + return 0; } diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h index 7c889c04604b..91a542df5791 100644 --- a/arch/arm/mach-rockchip/pm.h +++ b/arch/arm/mach-rockchip/pm.h @@ -63,6 +63,10 @@ static inline void rockchip_suspend_init(void) /* PMU_WAKEUP_CFG1 bits */ #define PMU_ARMINT_WAKEUP_EN BIT(0) +/* wait 30ms for OSC stable and 30ms for pmic stable */ +#define OSC_STABL_CNT_THRESH (32 * 30) +#define PMU_STABL_CNT_THRESH (32 * 30) + enum rk3288_pwr_mode_con { PMU_PWR_MODE_EN = 0, PMU_CLK_CORE_SRC_GATE_EN, From a0307d186f5015ee3d77e209e5c06190cbf02478 Mon Sep 17 00:00:00 2001 From: Chris Zhong Date: Mon, 9 Feb 2015 21:12:23 +0800 Subject: [PATCH 3/3] ARM: rockchip: disable watchdog during suspend The watchdog clock should be disable in dw_wdt_suspend, but we set a dummy clock to watchdog for rk3288. So the watchdog will continue to work during suspend. And we switch the system clock to 32khz from 24Mhz, during suspend, so the watchdog timer over count will increase to 755 times, about 12.5 hours, the original value is 60 seconds. So watchdog will reset the system over a night, but voltage are all incorrect, then it hang on reset. Signed-off-by: Chris Zhong Signed-off-by: Daniel Kurtz Reviewed-by: Doug Anderson Tested-by: Doug Anderson Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/pm.c | 11 ++++++++--- arch/arm/mach-rockchip/pm.h | 2 ++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c index a3ab3979923c..b07d88602073 100644 --- a/arch/arm/mach-rockchip/pm.c +++ b/arch/arm/mach-rockchip/pm.c @@ -75,9 +75,13 @@ static void rk3288_slp_mode_set(int level) regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, &rk3288_pmu_pwr_mode_con); - /* set bit 8 so that system will resume to FAST_BOOT_ADDR */ + /* + * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR + * PCLK_WDT_GATE - disable WDT during suspend. + */ regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, - SGRF_FAST_BOOT_EN | SGRF_FAST_BOOT_EN_WRITE); + SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN + | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE); /* booting address of resuming system is from this register value */ regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR, @@ -122,7 +126,8 @@ static void rk3288_slp_mode_set_resume(void) rk3288_pmu_pwr_mode_con); regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, - rk3288_sgrf_soc_con0 | SGRF_FAST_BOOT_EN_WRITE); + rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE + | SGRF_FAST_BOOT_EN_WRITE); } static int rockchip_lpmode_enter(unsigned long arg) diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h index 91a542df5791..03ff31d8282d 100644 --- a/arch/arm/mach-rockchip/pm.h +++ b/arch/arm/mach-rockchip/pm.h @@ -50,6 +50,8 @@ static inline void rockchip_suspend_init(void) #define RK3288_SGRF_SOC_CON0 (0x0000) #define RK3288_SGRF_FAST_BOOT_ADDR (0x0120) +#define SGRF_PCLK_WDT_GATE BIT(6) +#define SGRF_PCLK_WDT_GATE_WRITE BIT(22) #define SGRF_FAST_BOOT_EN BIT(8) #define SGRF_FAST_BOOT_EN_WRITE BIT(24)