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https://github.com/torvalds/linux.git
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arm64: dts: qcom: lemans: Move PCIe devices into soc node
These PCIe devices with MMIO address should be inside soc node rather
than outside.
Fixes: 489f14be0e ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes")
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260331090147.18522-1-shengchao.guo@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Shawn Guo
Bjorn Andersson
parent
141d7ea503
commit
8222873cd4
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@ -2694,6 +2694,352 @@ mmss_noc: interconnect@17a0000 {
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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pcie0: pcie@1c00000 {
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compatible = "qcom,pcie-sa8775p";
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reg = <0x0 0x01c00000 0x0 0x3000>,
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<0x0 0x40000000 0x0 0xf20>,
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<0x0 0x40000f20 0x0 0xa8>,
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<0x0 0x40001000 0x0 0x4000>,
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<0x0 0x40100000 0x0 0x100000>,
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<0x0 0x01c03000 0x0 0x1000>;
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reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
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bus-range = <0x00 0xff>;
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dma-coherent;
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linux,pci-domain = <0>;
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num-lanes = <2>;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7",
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"global";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a";
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assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
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<0x100 &pcie_smmu 0x0001 0x1>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
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reset-names = "pci",
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"link_down";
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power-domains = <&gcc PCIE_0_GDSC>;
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phys = <&pcie0_phy>;
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phy-names = "pciephy";
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eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
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eq-presets-16gts = /bits/ 8 <0x55 0x55>;
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status = "disabled";
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pcieport0: pcie@0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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pcie0_ep: pcie-ep@1c00000 {
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compatible = "qcom,sa8775p-pcie-ep";
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reg = <0x0 0x01c00000 0x0 0x3000>,
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<0x0 0x40000000 0x0 0xf20>,
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<0x0 0x40000f20 0x0 0xa8>,
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<0x0 0x40001000 0x0 0x4000>,
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<0x0 0x40200000 0x0 0x1fe00000>,
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<0x0 0x01c03000 0x0 0x1000>,
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<0x0 0x40005000 0x0 0x2000>;
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reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
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"mmio", "dma";
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clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a";
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interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global", "doorbell", "dma";
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interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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dma-coherent;
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iommus = <&pcie_smmu 0x0000 0x7f>;
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resets = <&gcc GCC_PCIE_0_BCR>;
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reset-names = "core";
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power-domains = <&gcc PCIE_0_GDSC>;
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phys = <&pcie0_phy>;
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phy-names = "pciephy";
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num-lanes = <2>;
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linux,pci-domain = <0>;
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status = "disabled";
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};
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pcie0_phy: phy@1c04000 {
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compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
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reg = <0x0 0x1c04000 0x0 0x2000>;
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clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_CLKREF_EN>,
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<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_0_PIPE_CLK>,
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<&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"rchng",
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"pipe",
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"pipediv2";
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assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
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assigned-clock-rates = <100000000>;
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resets = <&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "phy";
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#clock-cells = <0>;
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clock-output-names = "pcie_0_pipe_clk";
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#phy-cells = <0>;
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status = "disabled";
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};
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pcie1: pcie@1c10000 {
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compatible = "qcom,pcie-sa8775p";
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reg = <0x0 0x01c10000 0x0 0x3000>,
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<0x0 0x60000000 0x0 0xf20>,
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<0x0 0x60000f20 0x0 0xa8>,
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<0x0 0x60001000 0x0 0x4000>,
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<0x0 0x60100000 0x0 0x100000>,
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<0x0 0x01c13000 0x0 0x1000>;
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reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
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bus-range = <0x00 0xff>;
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dma-coherent;
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linux,pci-domain = <1>;
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num-lanes = <4>;
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interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7",
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"global";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a";
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assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
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<0x100 &pcie_smmu 0x0081 0x1>;
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resets = <&gcc GCC_PCIE_1_BCR>,
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<&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
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reset-names = "pci",
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"link_down";
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power-domains = <&gcc PCIE_1_GDSC>;
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phys = <&pcie1_phy>;
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phy-names = "pciephy";
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eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
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eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
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status = "disabled";
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pcie@0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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pcie1_ep: pcie-ep@1c10000 {
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compatible = "qcom,sa8775p-pcie-ep";
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reg = <0x0 0x01c10000 0x0 0x3000>,
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<0x0 0x60000000 0x0 0xf20>,
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<0x0 0x60000f20 0x0 0xa8>,
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<0x0 0x60001000 0x0 0x4000>,
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<0x0 0x60200000 0x0 0x1fe00000>,
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<0x0 0x01c13000 0x0 0x1000>,
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<0x0 0x60005000 0x0 0x2000>;
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reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
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"mmio", "dma";
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clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a";
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interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global", "doorbell", "dma";
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interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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dma-coherent;
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iommus = <&pcie_smmu 0x80 0x7f>;
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resets = <&gcc GCC_PCIE_1_BCR>;
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reset-names = "core";
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power-domains = <&gcc PCIE_1_GDSC>;
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phys = <&pcie1_phy>;
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phy-names = "pciephy";
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num-lanes = <4>;
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linux,pci-domain = <1>;
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status = "disabled";
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};
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pcie1_phy: phy@1c14000 {
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compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
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reg = <0x0 0x1c14000 0x0 0x4000>;
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clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_CLKREF_EN>,
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<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_1_PIPE_CLK>,
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<&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"rchng",
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"pipe",
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"pipediv2";
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assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
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assigned-clock-rates = <100000000>;
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resets = <&gcc GCC_PCIE_1_PHY_BCR>;
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reset-names = "phy";
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#clock-cells = <0>;
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clock-output-names = "pcie_1_pipe_clk";
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#phy-cells = <0>;
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status = "disabled";
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};
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ufs_mem_hc: ufshc@1d84000 {
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compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
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reg = <0x0 0x01d84000 0x0 0x3000>;
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@ -8836,350 +9182,4 @@ turing_llm_tpdm_out: endpoint {
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};
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};
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};
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pcie0: pcie@1c00000 {
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compatible = "qcom,pcie-sa8775p";
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reg = <0x0 0x01c00000 0x0 0x3000>,
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<0x0 0x40000000 0x0 0xf20>,
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<0x0 0x40000f20 0x0 0xa8>,
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<0x0 0x40001000 0x0 0x4000>,
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<0x0 0x40100000 0x0 0x100000>,
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<0x0 0x01c03000 0x0 0x1000>;
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reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
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bus-range = <0x00 0xff>;
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dma-coherent;
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linux,pci-domain = <0>;
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num-lanes = <2>;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7",
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"global";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
|
||||
|
||||
clock-names = "aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a";
|
||||
|
||||
assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
|
||||
interconnect-names = "pcie-mem", "cpu-pcie";
|
||||
|
||||
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
|
||||
<0x100 &pcie_smmu 0x0001 0x1>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>,
|
||||
<&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
|
||||
reset-names = "pci",
|
||||
"link_down";
|
||||
|
||||
power-domains = <&gcc PCIE_0_GDSC>;
|
||||
|
||||
phys = <&pcie0_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
|
||||
eq-presets-16gts = /bits/ 8 <0x55 0x55>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pcieport0: pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_ep: pcie-ep@1c00000 {
|
||||
compatible = "qcom,sa8775p-pcie-ep";
|
||||
reg = <0x0 0x01c00000 0x0 0x3000>,
|
||||
<0x0 0x40000000 0x0 0xf20>,
|
||||
<0x0 0x40000f20 0x0 0xa8>,
|
||||
<0x0 0x40001000 0x0 0x4000>,
|
||||
<0x0 0x40200000 0x0 0x1fe00000>,
|
||||
<0x0 0x01c03000 0x0 0x1000>,
|
||||
<0x0 0x40005000 0x0 0x2000>;
|
||||
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
|
||||
"mmio", "dma";
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
|
||||
|
||||
clock-names = "aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a";
|
||||
|
||||
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
interrupt-names = "global", "doorbell", "dma";
|
||||
|
||||
interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
|
||||
interconnect-names = "pcie-mem", "cpu-pcie";
|
||||
|
||||
dma-coherent;
|
||||
iommus = <&pcie_smmu 0x0000 0x7f>;
|
||||
resets = <&gcc GCC_PCIE_0_BCR>;
|
||||
reset-names = "core";
|
||||
power-domains = <&gcc PCIE_0_GDSC>;
|
||||
phys = <&pcie0_phy>;
|
||||
phy-names = "pciephy";
|
||||
num-lanes = <2>;
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie0_phy: phy@1c04000 {
|
||||
compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
|
||||
reg = <0x0 0x1c04000 0x0 0x2000>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_CLKREF_EN>,
|
||||
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
|
||||
<&gcc GCC_PCIE_0_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
|
||||
clock-names = "aux",
|
||||
"cfg_ahb",
|
||||
"ref",
|
||||
"rchng",
|
||||
"pipe",
|
||||
"pipediv2";
|
||||
|
||||
assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
|
||||
reset-names = "phy";
|
||||
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "pcie_0_pipe_clk";
|
||||
|
||||
#phy-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie1: pcie@1c10000 {
|
||||
compatible = "qcom,pcie-sa8775p";
|
||||
reg = <0x0 0x01c10000 0x0 0x3000>,
|
||||
<0x0 0x60000000 0x0 0xf20>,
|
||||
<0x0 0x60000f20 0x0 0xa8>,
|
||||
<0x0 0x60001000 0x0 0x4000>,
|
||||
<0x0 0x60100000 0x0 0x100000>,
|
||||
<0x0 0x01c13000 0x0 0x1000>;
|
||||
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
dma-coherent;
|
||||
|
||||
linux,pci-domain = <1>;
|
||||
num-lanes = <4>;
|
||||
|
||||
interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0",
|
||||
"msi1",
|
||||
"msi2",
|
||||
"msi3",
|
||||
"msi4",
|
||||
"msi5",
|
||||
"msi6",
|
||||
"msi7",
|
||||
"global";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
|
||||
|
||||
clock-names = "aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a";
|
||||
|
||||
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
|
||||
interconnect-names = "pcie-mem", "cpu-pcie";
|
||||
|
||||
iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
|
||||
<0x100 &pcie_smmu 0x0081 0x1>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_1_BCR>,
|
||||
<&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
|
||||
reset-names = "pci",
|
||||
"link_down";
|
||||
|
||||
power-domains = <&gcc PCIE_1_GDSC>;
|
||||
|
||||
phys = <&pcie1_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
|
||||
eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_ep: pcie-ep@1c10000 {
|
||||
compatible = "qcom,sa8775p-pcie-ep";
|
||||
reg = <0x0 0x01c10000 0x0 0x3000>,
|
||||
<0x0 0x60000000 0x0 0xf20>,
|
||||
<0x0 0x60000f20 0x0 0xa8>,
|
||||
<0x0 0x60001000 0x0 0x4000>,
|
||||
<0x0 0x60200000 0x0 0x1fe00000>,
|
||||
<0x0 0x01c13000 0x0 0x1000>,
|
||||
<0x0 0x60005000 0x0 0x2000>;
|
||||
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
|
||||
"mmio", "dma";
|
||||
|
||||
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
|
||||
|
||||
clock-names = "aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a";
|
||||
|
||||
interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
interrupt-names = "global", "doorbell", "dma";
|
||||
|
||||
interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
|
||||
interconnect-names = "pcie-mem", "cpu-pcie";
|
||||
|
||||
dma-coherent;
|
||||
iommus = <&pcie_smmu 0x80 0x7f>;
|
||||
resets = <&gcc GCC_PCIE_1_BCR>;
|
||||
reset-names = "core";
|
||||
power-domains = <&gcc PCIE_1_GDSC>;
|
||||
phys = <&pcie1_phy>;
|
||||
phy-names = "pciephy";
|
||||
num-lanes = <4>;
|
||||
linux,pci-domain = <1>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie1_phy: phy@1c14000 {
|
||||
compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
|
||||
reg = <0x0 0x1c14000 0x0 0x4000>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_CLKREF_EN>,
|
||||
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
|
||||
<&gcc GCC_PCIE_1_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
|
||||
clock-names = "aux",
|
||||
"cfg_ahb",
|
||||
"ref",
|
||||
"rchng",
|
||||
"pipe",
|
||||
"pipediv2";
|
||||
|
||||
assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
|
||||
reset-names = "phy";
|
||||
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "pcie_1_pipe_clk";
|
||||
|
||||
#phy-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user