From 2d33ced5500320f55fd2f63364f1212ba19453e8 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 8 Aug 2017 12:24:09 +0100 Subject: [PATCH 1/9] ARM: dts: r8a7743: Add I2C DT support Add the I2C[0-5] devices to the r8a7743 device tree. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 97 ++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index f62e8587f1a8..ce80a26c421a 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -18,6 +18,15 @@ / { #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -314,6 +323,94 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH dma-channels = <15>; }; + /* The memory map in the User's Manual maps the cores to bus + * numbers + */ + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7743", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7743", "renesas,rcar-gen2-scifa", "renesas,scifa"; From 95b94ed9abb58d2f5372a980a0af037e76c0beaf Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 15 Apr 2017 23:18:26 +0300 Subject: [PATCH 2/9] ARM: dts: r8a7745: add PFC support Define the generic R8A7745 part of the PFC device node. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 354534cdc588..aff90dfb8b32 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for the r8a7745 SoC * - * Copyright (C) 2016 Cogent Embedded Inc. + * Copyright (C) 2016-2017 Cogent Embedded Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -123,6 +123,11 @@ sysc: system-controller@e6180000 { #power-domain-cells = <1>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7745"; + reg = <0 0xe6060000 0 0x11c>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7745", "renesas,rcar-dmac"; From 8774ee66ae478fab7d57bd9f6cd5a27981a4be92 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 15 Apr 2017 23:18:27 +0300 Subject: [PATCH 3/9] ARM: dts: sk-rzg1e: add SCIF2 pins Add the (previously omitted) SCIF2 pin data to the SK-RZG1E board's device tree. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts index 97840b340197..0cd908796055 100644 --- a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts +++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts @@ -1,7 +1,7 @@ /* * Device Tree Source for the SK-RZG1E board * - * Copyright (C) 2016 Cogent Embedded, Inc. + * Copyright (C) 2016-2017 Cogent Embedded, Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -34,7 +34,17 @@ &extal_clk { clock-frequency = <20000000>; }; +&pfc { + scif2_pins: scif2 { + groups = "scif2_data"; + function = "scif2"; + }; +}; + &scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + status = "okay"; }; From 485a40469cf05d7948e1d8c9dbd9058044ded91c Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 15 Apr 2017 23:18:28 +0300 Subject: [PATCH 4/9] ARM: dts: sk-rzg1e: add Ether pins Add the (previously omitted) Ether/PHY pin data to the SK-RZG1E board's device tree. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts index 0cd908796055..b4d679b04ad6 100644 --- a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts +++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts @@ -39,6 +39,16 @@ scif2_pins: scif2 { groups = "scif2_data"; function = "scif2"; }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq8"; + function = "intc"; + }; }; &scif2 { @@ -49,6 +59,9 @@ &scif2 { }; ðer { + pinctrl-0 = <ðer_pins &phy1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; renesas,ether-link-active-low; status = "okay"; From 02a5ab18d366223893d634b0992f6434300bee32 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Sun, 30 Jul 2017 15:07:42 +0200 Subject: [PATCH 5/9] ARM: dts: koelsch: Add CEC clock for HDMI transmitter The adv7511 on the Koelsch board has a 12 MHz fixed clock for the CEC block. Specify this in the dts to enable CEC support. Signed-off-by: Hans Verkuil Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index dc8ed02de707..0ce0b278e1cb 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -642,11 +642,19 @@ adv7180: endpoint { }; }; + cec_clock: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + hdmi@39 { compatible = "adi,adv7511w"; reg = <0x39>; interrupt-parent = <&gpio3>; interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cec_clock>; + clock-names = "cec"; adi,input-depth = <8>; adi,input-colorspace = "rgb"; From 60dce695b097a52e6ea5874aa80301f2e4ac627a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 8 Aug 2017 11:56:32 +0100 Subject: [PATCH 6/9] ARM: dts: r8a7743: Add APMU node and second CPU core Add DT nodes for the Advanced Power Management Unit (APMU) and the second CPU core. Use the enable-method to point out that the APMU should be used for SMP support. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index ce80a26c421a..ec9db0fcffc6 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -30,6 +30,7 @@ aliases { cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -41,6 +42,15 @@ cpu0: cpu@0 { next-level-cache = <&L2_CA15>; }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1500000000>; + power-domains = <&sysc R8A7743_PD_CA15_CPU1>; + next-level-cache = <&L2_CA15>; + }; + L2_CA15: cache-controller-0 { compatible = "cache"; cache-unified; @@ -57,6 +67,12 @@ soc { #size-cells = <2>; ranges; + apmu@e6152000 { + compatible = "renesas,r8a7743-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; From 0417814ea140d1bc7e8a5d54e95e17a234b34e49 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 8 Aug 2017 11:56:33 +0100 Subject: [PATCH 7/9] ARM: dts: r8a7743: Add OPP table for frequency scaling Add needed information inside CPU0 for the generic cpufreq-cpu0 driver. - clock-latency = 300 us Approximate worst-case latency to do clock transition for every OPPs. Using an arbitrary safe value similar to r8a7791(R-Car M2) Soc. - operating-points = < kHz - uV > List of 6 operating points. All of them are using the same voltage since DVS is not supported in RZ/G1 Soc. Note:This also fixes the below errors seen on kernel logs [ 0.876877] cpu cpu0: dev_pm_opp_get_opp_count: OPP table not found (-19) [ 0.883727] cpu cpu1: cpufreq_init: failed to get clk: -2 Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index ec9db0fcffc6..14222c72f0e0 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -38,8 +38,17 @@ cpu0: cpu@0 { reg = <0>; clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; + clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7743_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; }; cpu1: cpu@1 { From faa63e832c427b7ba107291e9f07fa2f570c0835 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 9 Aug 2017 10:26:41 +0200 Subject: [PATCH 8/9] ARM: dts: r8a7790: Use R-Car SATA Gen2 fallback compat string Use newly added R-Car SATA Gen2 fallback compat string in the DT of the r8a7790 SoC. This should have no run-time effect as the driver matches against the per-SoC compat string before the fallback compat string is considered. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7790.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 167fd57aea68..16358bf8d1db 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -873,7 +873,7 @@ avb: ethernet@e6800000 { }; sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7790"; + compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata"; reg = <0 0xee300000 0 0x2000>; interrupts = ; clocks = <&mstp8_clks R8A7790_CLK_SATA0>; @@ -882,7 +882,7 @@ sata0: sata@ee300000 { }; sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7790"; + compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata"; reg = <0 0xee500000 0 0x2000>; interrupts = ; clocks = <&mstp8_clks R8A7790_CLK_SATA1>; From a4bc74d570a79dbfeb64766b130c0113ac39ec3e Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 9 Aug 2017 10:26:42 +0200 Subject: [PATCH 9/9] ARM: dts: r8a7791: Use R-Car SATA Gen2 fallback compat string Use newly added R-Car SATA Gen2 fallback compat string in the DT of the r8a7791 SoC. This should have no run-time effect as the driver matches against the per-SoC compat string before the fallback compat string is considered. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7791.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index ea4a8147d995..f1d1a9772153 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -933,7 +933,7 @@ avb: ethernet@e6800000 { }; sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7791"; + compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; reg = <0 0xee300000 0 0x2000>; interrupts = ; clocks = <&mstp8_clks R8A7791_CLK_SATA0>; @@ -942,7 +942,7 @@ sata0: sata@ee300000 { }; sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7791"; + compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; reg = <0 0xee500000 0 0x2000>; interrupts = ; clocks = <&mstp8_clks R8A7791_CLK_SATA1>;