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i2c: tegra: Update Tegra256 timing parameters

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Update the timing parameters of Tegra256 so that the signals are complaint
with the I2C specification for SCL low time.

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
This commit is contained in:
Akhil R 2025-11-18 19:36:17 +05:30 committed by Wolfram Sang
parent 8b80b61e6f
commit 81d4c5350f
1 changed files with 7 additions and 8 deletions
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15
drivers/i2c/busses/i2c-tegra.c
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@ -1684,7 +1684,7 @@ static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
.clk_divisor_hs_mode = 7,
.clk_divisor_std_mode = 0x7a,
.clk_divisor_fast_mode = 0x40,
.clk_divisor_fast_plus_mode = 0x19,
.clk_divisor_fast_plus_mode = 0x14,
.has_config_load_reg = true,
.has_multi_master_mode = true,
.has_slcg_override_reg = true,
@ -1695,14 +1695,13 @@ static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
.has_apb_dma = false,
.tlow_std_mode = 0x8,
.thigh_std_mode = 0x7,
.tlow_fast_mode = 0x3,
.thigh_fast_mode = 0x3,
.tlow_fastplus_mode = 0x3,
.thigh_fastplus_mode = 0x3,
.tlow_fast_mode = 0x4,
.thigh_fast_mode = 0x2,
.tlow_fastplus_mode = 0x4,
.thigh_fastplus_mode = 0x4,
.setup_hold_time_std_mode = 0x08080808,
.setup_hold_time_fast_mode = 0x02020202,
.setup_hold_time_fastplus_mode = 0x02020202,
.setup_hold_time_hs_mode = 0x090909,
.setup_hold_time_fast_mode = 0x04010101,
.setup_hold_time_fastplus_mode = 0x04020202,
.has_interface_timing_reg = true,
};