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drm/i915/cmtg: Add CMTG scan line programming

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Enable the hardware based guardband calculations which allows
DC3co to remain enabled when timings are changing from one fixed
refresh rate to another fixed refresh rate.

Bspec: 75253
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patch.msgid.link/20260615200339.885190-20-animesh.manna@intel.com
This commit is contained in:
Dibin Moolakadan Subrahmanian 2026-06-16 01:33:36 +05:30 committed by Animesh Manna
parent 9570e945f2
commit 81c7da958f
2 changed files with 8 additions and 0 deletions
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2
drivers/gpu/drm/i915/display/intel_cmtg.c
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@ -195,6 +195,7 @@ void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
CMTG_SECONDARY_MODE, 0);
intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), CMTG_HW_GB_ENABLE, 0);
intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_ENABLE, 0);
@ -361,6 +362,7 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
return;
intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), 0, CMTG_HW_GB_ENABLE);
crtc->cmtg.enabled = true;
drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
}

6
drivers/gpu/drm/i915/display/intel_cmtg_regs.h
View File

@ -32,4 +32,10 @@
#define CMTG_HW_GB_DC5_EXIT_LATENCY_MASK REG_GENMASK(27, 16)
#define CMTG_HW_GB_UP_LW_BG_DIFF_MASK REG_GENMASK(31, 28)
#define _CMTG_SCANLINE_GB1_A 0x456A0
#define _CMTG_SCANLINE_GB1_B 0x456C0
#define CMTG_SCANLINE_GB1(trans) _MMIO_TRANS((trans), \
_CMTG_SCANLINE_GB1_A, _CMTG_SCANLINE_GB1_B)
#define CMTG_HW_GB_ENABLE REG_BIT(31)
#endif /* __INTEL_CMTG_REGS_H__ */