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drm fixes for 6.19-final

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amdgpu:
 - MES 11 old firmware compatibility fix
 - ASPM fix
 - DC LUT fixes
 
 amdkfd:
 - Fix possible double deletion of validate list
 
 xe:
 - Fix topology query pointer advance
 - A couple of kerneldoc fixes
 - Disable D3Cold for BMG only on specific platforms
 - Fix CFI violation in debugfs access
 
 nouveau:
 - Revert adding atomic commit functions as it regresses pre-nv50.
 - Fix suspend/resume bugs exposed by enabling 570 firmware.
 
 gma500:
 - Revert a regression caused by vblank changes.
 
 mgag200:
 - Replace a busy loop with a polling loop to fix that blocking 1 cpu for 300 ms roughly every 20 minutes.
 
 bridge:
 - imx8mp-hdmi-pa: Use runtime pm to fix a bug in channel ordering.
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Merge tag 'drm-fixes-2026-02-06' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
 "The usual xe/amdgpu selection, and a couple of misc changes for
  gma500, mgag200 and bridge. There is a nouveau revert, and also a set
  of changes that fix a regression since we moved to 570 firmware.
  Suspend/resume was broken on a bunch of GPUs. The fix looks big, but
  it's mostly just refactoring to pass an extra bit down the nouveau
  abstractions to the firmware command.

  amdgpu:
   - MES 11 old firmware compatibility fix
   - ASPM fix
   - DC LUT fixes

  amdkfd:
   - Fix possible double deletion of validate list

  xe:
   - Fix topology query pointer advance
   - A couple of kerneldoc fixes
   - Disable D3Cold for BMG only on specific platforms
   - Fix CFI violation in debugfs access

  nouveau:
   - Revert adding atomic commit functions as it regresses pre-nv50
   - Fix suspend/resume bugs exposed by enabling 570 firmware

  gma500:
   - Revert a regression caused by vblank changes

  mgag200:
   - Replace a busy loop with a polling loop to fix that blocking 1 cpu
     for 300 ms roughly every 20 minutes

bridge:
   - imx8mp-hdmi-pa: Use runtime pm to fix a bug in channel ordering"

* tag 'drm-fixes-2026-02-06' of https://gitlab.freedesktop.org/drm/kernel:
  drm/xe/guc: Fix CFI violation in debugfs access.
  drm/bridge: imx8mp-hdmi-pai: enable PM runtime
  drm/xe/pm: Disable D3Cold for BMG only on specific platforms
  drm/xe: Fix kerneldoc for xe_tlb_inval_job_alloc_dep
  drm/xe: Fix kerneldoc for xe_gt_tlb_inval_init_early
  drm/xe: Fix kerneldoc for xe_migrate_exec_queue
  drm/xe/query: Fix topology query pointer advance
  drm/mgag200: fix mgag200_bmc_stop_scanout()
  nouveau/gsp: fix suspend/resume regression on r570 firmware
  nouveau: add a third state to the fini handler.
  nouveau/gsp: use rpc sequence numbers properly.
  drm/amdgpu: Fix double deletion of validate_list
  drm/amd/display: remove assert around dpp_base replacement
  drm/amd/display: extend delta clamping logic to CM3 LUT helper
  drm/amd/display: fix wrong color value mapping on MCM shaper LUT
  Revert "drm/amd: Check if ASPM is enabled from PCIe subsystem"
  drm/amd: Set minimum version for set_hw_resource_1 on gfx11 to 0x52
  Revert "drm/gma500: use drm_crtc_vblank_crtc()"
  Revert "drm/nouveau/disp: Set drm_mode_config_funcs.atomic_(check|commit)"
This commit is contained in:
Linus Torvalds 2026-02-05 19:56:47 -08:00
commit 8185461e53
82 changed files with 290 additions and 189 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
View File

@ -1920,21 +1920,21 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
/* Make sure restore workers don't access the BO any more */
mutex_lock(&process_info->lock);
list_del(&mem->validate_list);
if (!list_empty(&mem->validate_list))
list_del_init(&mem->validate_list);
mutex_unlock(&process_info->lock);
/* Cleanup user pages and MMU notifiers */
if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
amdgpu_hmm_unregister(mem->bo);
mutex_lock(&process_info->notifier_lock);
amdgpu_hmm_range_free(mem->range);
mutex_unlock(&process_info->notifier_lock);
}
ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
if (unlikely(ret))
return ret;
/* Cleanup user pages and MMU notifiers */
if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
amdgpu_hmm_unregister(mem->bo);
amdgpu_hmm_range_free(mem->range);
mem->range = NULL;
}
amdgpu_amdkfd_remove_eviction_fence(mem->bo,
process_info->eviction_fence);
pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,

3
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View File

@ -2405,9 +2405,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
return -ENODEV;
}
if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
amdgpu_aspm = 0;
if (amdgpu_virtual_display ||
amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK))
supports_atomic = true;

2
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
View File

@ -1671,7 +1671,7 @@ static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
if (r)
goto failure;
if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x50) {
if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x52) {
r = mes_v11_0_set_hw_resources_1(&adev->mes);
if (r) {
DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);

37
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
View File

@ -105,9 +105,12 @@ void cm_helper_program_gamcor_xfer_func(
#define NUMBER_REGIONS 32
#define NUMBER_SW_SEGMENTS 16
bool cm3_helper_translate_curve_to_hw_format(
const struct dc_transfer_func *output_tf,
struct pwl_params *lut_params, bool fixpoint)
#define DC_LOGGER \
ctx->logger
bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx,
const struct dc_transfer_func *output_tf,
struct pwl_params *lut_params, bool fixpoint)
{
struct curve_points3 *corner_points;
struct pwl_result_data *rgb_resulted;
@ -163,6 +166,11 @@ bool cm3_helper_translate_curve_to_hw_format(
hw_points += (1 << seg_distr[k]);
}
// DCN3+ have 257 pts in lieu of no separate slope registers
// Prior HW had 256 base+slope pairs
// Shaper LUT (i.e. fixpoint == true) is still 256 bases and 256 deltas
hw_points = fixpoint ? (hw_points - 1) : hw_points;
j = 0;
for (k = 0; k < (region_end - region_start); k++) {
increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
@ -223,8 +231,6 @@ bool cm3_helper_translate_curve_to_hw_format(
corner_points[1].green.slope = dc_fixpt_zero;
corner_points[1].blue.slope = dc_fixpt_zero;
// DCN3+ have 257 pts in lieu of no separate slope registers
// Prior HW had 256 base+slope pairs
lut_params->hw_points_num = hw_points + 1;
k = 0;
@ -248,6 +254,10 @@ bool cm3_helper_translate_curve_to_hw_format(
if (fixpoint == true) {
i = 1;
while (i != hw_points + 2) {
uint32_t red_clamp;
uint32_t green_clamp;
uint32_t blue_clamp;
if (i >= hw_points) {
if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
rgb_plus_1->red = dc_fixpt_add(rgb->red,
@ -260,9 +270,20 @@ bool cm3_helper_translate_curve_to_hw_format(
rgb_minus_1->delta_blue);
}
rgb->delta_red_reg = dc_fixpt_clamp_u0d10(rgb->delta_red);
rgb->delta_green_reg = dc_fixpt_clamp_u0d10(rgb->delta_green);
rgb->delta_blue_reg = dc_fixpt_clamp_u0d10(rgb->delta_blue);
rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
red_clamp = dc_fixpt_clamp_u0d14(rgb->delta_red);
green_clamp = dc_fixpt_clamp_u0d14(rgb->delta_green);
blue_clamp = dc_fixpt_clamp_u0d14(rgb->delta_blue);
if (red_clamp >> 10 || green_clamp >> 10 || blue_clamp >> 10)
DC_LOG_ERROR("Losing delta precision while programming shaper LUT.");
rgb->delta_red_reg = red_clamp & 0x3ff;
rgb->delta_green_reg = green_clamp & 0x3ff;
rgb->delta_blue_reg = blue_clamp & 0x3ff;
rgb->red_reg = dc_fixpt_clamp_u0d14(rgb->red);
rgb->green_reg = dc_fixpt_clamp_u0d14(rgb->green);
rgb->blue_reg = dc_fixpt_clamp_u0d14(rgb->blue);

2
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h
View File

@ -59,7 +59,7 @@ void cm_helper_program_gamcor_xfer_func(
const struct pwl_params *params,
const struct dcn3_xfer_func_reg *reg);
bool cm3_helper_translate_curve_to_hw_format(
bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx,
const struct dc_transfer_func *output_tf,
struct pwl_params *lut_params, bool fixpoint);

9
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
View File

@ -239,7 +239,7 @@ bool dcn30_set_blend_lut(
if (plane_state->blend_tf.type == TF_TYPE_HWPWL)
blend_lut = &plane_state->blend_tf.pwl;
else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {
result = cm3_helper_translate_curve_to_hw_format(
result = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,
&plane_state->blend_tf, &dpp_base->regamma_params, false);
if (!result)
return result;
@ -334,8 +334,9 @@ bool dcn30_set_input_transfer_func(struct dc *dc,
if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL)
params = &plane_state->in_transfer_func.pwl;
else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS &&
cm3_helper_translate_curve_to_hw_format(&plane_state->in_transfer_func,
&dpp_base->degamma_params, false))
cm3_helper_translate_curve_to_hw_format(plane_state->ctx,
&plane_state->in_transfer_func,
&dpp_base->degamma_params, false))
params = &dpp_base->degamma_params;
result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
@ -406,7 +407,7 @@ bool dcn30_set_output_transfer_func(struct dc *dc,
params = &stream->out_transfer_func.pwl;
else if (pipe_ctx->stream->out_transfer_func.type ==
TF_TYPE_DISTRIBUTED_POINTS &&
cm3_helper_translate_curve_to_hw_format(
cm3_helper_translate_curve_to_hw_format(stream->ctx,
&stream->out_transfer_func,
&mpc->blender_params, false))
params = &mpc->blender_params;

18
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
View File

@ -486,8 +486,9 @@ bool dcn32_set_mcm_luts(
if (plane_state->blend_tf.type == TF_TYPE_HWPWL)
lut_params = &plane_state->blend_tf.pwl;
else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {
result = cm3_helper_translate_curve_to_hw_format(&plane_state->blend_tf,
&dpp_base->regamma_params, false);
result = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,
&plane_state->blend_tf,
&dpp_base->regamma_params, false);
if (!result)
return result;
@ -501,9 +502,9 @@ bool dcn32_set_mcm_luts(
lut_params = &plane_state->in_shaper_func.pwl;
else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {
// TODO: dpp_base replace
ASSERT(false);
cm3_helper_translate_curve_to_hw_format(&plane_state->in_shaper_func,
&dpp_base->shaper_params, true);
cm3_helper_translate_curve_to_hw_format(plane_state->ctx,
&plane_state->in_shaper_func,
&dpp_base->shaper_params, true);
lut_params = &dpp_base->shaper_params;
}
@ -543,8 +544,9 @@ bool dcn32_set_input_transfer_func(struct dc *dc,
if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL)
params = &plane_state->in_transfer_func.pwl;
else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS &&
cm3_helper_translate_curve_to_hw_format(&plane_state->in_transfer_func,
&dpp_base->degamma_params, false))
cm3_helper_translate_curve_to_hw_format(plane_state->ctx,
&plane_state->in_transfer_func,
&dpp_base->degamma_params, false))
params = &dpp_base->degamma_params;
dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
@ -575,7 +577,7 @@ bool dcn32_set_output_transfer_func(struct dc *dc,
params = &stream->out_transfer_func.pwl;
else if (pipe_ctx->stream->out_transfer_func.type ==
TF_TYPE_DISTRIBUTED_POINTS &&
cm3_helper_translate_curve_to_hw_format(
cm3_helper_translate_curve_to_hw_format(stream->ctx,
&stream->out_transfer_func,
&mpc->blender_params, false))
params = &mpc->blender_params;

16
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
View File

@ -430,7 +430,7 @@ void dcn401_populate_mcm_luts(struct dc *dc,
if (mcm_luts.lut1d_func->type == TF_TYPE_HWPWL)
m_lut_params.pwl = &mcm_luts.lut1d_func->pwl;
else if (mcm_luts.lut1d_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
rval = cm3_helper_translate_curve_to_hw_format(
rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx,
mcm_luts.lut1d_func,
&dpp_base->regamma_params, false);
m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL;
@ -450,7 +450,7 @@ void dcn401_populate_mcm_luts(struct dc *dc,
m_lut_params.pwl = &mcm_luts.shaper->pwl;
else if (mcm_luts.shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
ASSERT(false);
rval = cm3_helper_translate_curve_to_hw_format(
rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx,
mcm_luts.shaper,
&dpp_base->regamma_params, true);
m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL;
@ -627,8 +627,9 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
if (plane_state->blend_tf.type == TF_TYPE_HWPWL)
lut_params = &plane_state->blend_tf.pwl;
else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {
rval = cm3_helper_translate_curve_to_hw_format(&plane_state->blend_tf,
&dpp_base->regamma_params, false);
rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,
&plane_state->blend_tf,
&dpp_base->regamma_params, false);
lut_params = rval ? &dpp_base->regamma_params : NULL;
}
result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
@ -639,8 +640,9 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
lut_params = &plane_state->in_shaper_func.pwl;
else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {
// TODO: dpp_base replace
rval = cm3_helper_translate_curve_to_hw_format(&plane_state->in_shaper_func,
&dpp_base->shaper_params, true);
rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx,
&plane_state->in_shaper_func,
&dpp_base->shaper_params, true);
lut_params = rval ? &dpp_base->shaper_params : NULL;
}
result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
@ -674,7 +676,7 @@ bool dcn401_set_output_transfer_func(struct dc *dc,
params = &stream->out_transfer_func.pwl;
else if (pipe_ctx->stream->out_transfer_func.type ==
TF_TYPE_DISTRIBUTED_POINTS &&
cm3_helper_translate_curve_to_hw_format(
cm3_helper_translate_curve_to_hw_format(stream->ctx,
&stream->out_transfer_func,
&mpc->blender_params, false))
params = &mpc->blender_params;

15
drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c
View File

@ -8,6 +8,7 @@
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <drm/bridge/dw_hdmi.h>
#include <sound/asoundef.h>
@ -33,6 +34,7 @@
struct imx8mp_hdmi_pai {
struct regmap *regmap;
struct device *dev;
};
static void imx8mp_hdmi_pai_enable(struct dw_hdmi *dw_hdmi, int channel,
@ -43,6 +45,9 @@ static void imx8mp_hdmi_pai_enable(struct dw_hdmi *dw_hdmi, int channel,
struct imx8mp_hdmi_pai *hdmi_pai = pdata->priv_audio;
int val;
if (pm_runtime_resume_and_get(hdmi_pai->dev) < 0)
return;
/* PAI set control extended */
val = WTMK_HIGH(3) | WTMK_LOW(3);
val |= NUM_CH(channel);
@ -85,6 +90,8 @@ static void imx8mp_hdmi_pai_disable(struct dw_hdmi *dw_hdmi)
/* Stop PAI */
regmap_write(hdmi_pai->regmap, HTX_PAI_CTRL, 0);
pm_runtime_put_sync(hdmi_pai->dev);
}
static const struct regmap_config imx8mp_hdmi_pai_regmap_config = {
@ -101,6 +108,7 @@ static int imx8mp_hdmi_pai_bind(struct device *dev, struct device *master, void
struct imx8mp_hdmi_pai *hdmi_pai;
struct resource *res;
void __iomem *base;
int ret;
hdmi_pai = devm_kzalloc(dev, sizeof(*hdmi_pai), GFP_KERNEL);
if (!hdmi_pai)
@ -121,6 +129,13 @@ static int imx8mp_hdmi_pai_bind(struct device *dev, struct device *master, void
plat_data->disable_audio = imx8mp_hdmi_pai_disable;
plat_data->priv_audio = hdmi_pai;
hdmi_pai->dev = dev;
ret = devm_pm_runtime_enable(dev);
if (ret < 0) {
dev_err(dev, "failed to enable PM runtime: %d\n", ret);
return ret;
}
return 0;
}

36
drivers/gpu/drm/gma500/psb_irq.c
View File

@ -250,7 +250,6 @@ static irqreturn_t gma_irq_handler(int irq, void *arg)
void gma_irq_preinstall(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
struct drm_crtc *crtc;
unsigned long irqflags;
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
@ -261,15 +260,10 @@ void gma_irq_preinstall(struct drm_device *dev)
PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
drm_for_each_crtc(crtc, dev) {
struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
if (vblank->enabled) {
u32 mask = drm_crtc_index(crtc) ? _PSB_VSYNC_PIPEB_FLAG :
_PSB_VSYNC_PIPEA_FLAG;
dev_priv->vdc_irq_mask |= mask;
}
}
if (dev->vblank[0].enabled)
dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
if (dev->vblank[1].enabled)
dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
/* Revisit this area - want per device masks ? */
if (dev_priv->ops->hotplug)
@ -284,8 +278,8 @@ void gma_irq_preinstall(struct drm_device *dev)
void gma_irq_postinstall(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
struct drm_crtc *crtc;
unsigned long irqflags;
unsigned int i;
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
@ -298,13 +292,11 @@ void gma_irq_postinstall(struct drm_device *dev)
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
drm_for_each_crtc(crtc, dev) {
struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
if (vblank->enabled)
gma_enable_pipestat(dev_priv, drm_crtc_index(crtc), PIPE_VBLANK_INTERRUPT_ENABLE);
for (i = 0; i < dev->num_crtcs; ++i) {
if (dev->vblank[i].enabled)
gma_enable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
else
gma_disable_pipestat(dev_priv, drm_crtc_index(crtc), PIPE_VBLANK_INTERRUPT_ENABLE);
gma_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
}
if (dev_priv->ops->hotplug_enable)
@ -345,8 +337,8 @@ void gma_irq_uninstall(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
struct pci_dev *pdev = to_pci_dev(dev->dev);
struct drm_crtc *crtc;
unsigned long irqflags;
unsigned int i;
if (!dev_priv->irq_enabled)
return;
@ -358,11 +350,9 @@ void gma_irq_uninstall(struct drm_device *dev)
PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
drm_for_each_crtc(crtc, dev) {
struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
if (vblank->enabled)
gma_disable_pipestat(dev_priv, drm_crtc_index(crtc), PIPE_VBLANK_INTERRUPT_ENABLE);
for (i = 0; i < dev->num_crtcs; ++i) {
if (dev->vblank[i].enabled)
gma_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
}
dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |

31
drivers/gpu/drm/mgag200/mgag200_bmc.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_edid.h>
@ -12,7 +13,7 @@
void mgag200_bmc_stop_scanout(struct mga_device *mdev)
{
u8 tmp;
int iter_max;
int ret;
/*
* 1 - The first step is to inform the BMC of an upcoming mode
@ -42,30 +43,22 @@ void mgag200_bmc_stop_scanout(struct mga_device *mdev)
/*
* 3a- The third step is to verify if there is an active scan.
* We are waiting for a 0 on remhsyncsts <XSPAREREG<0>).
* We are waiting for a 0 on remhsyncsts (<XSPAREREG<0>).
*/
iter_max = 300;
while (!(tmp & 0x1) && iter_max) {
WREG8(DAC_INDEX, MGA1064_SPAREREG);
tmp = RREG8(DAC_DATA);
udelay(1000);
iter_max--;
}
ret = read_poll_timeout(RREG_DAC, tmp, !(tmp & 0x1),
1000, 300000, false,
MGA1064_SPAREREG);
if (ret == -ETIMEDOUT)
return;
/*
* 3b- This step occurs only if the remove is actually
* 3b- This step occurs only if the remote BMC is actually
* scanning. We are waiting for the end of the frame which is
* a 1 on remvsyncsts (XSPAREREG<1>)
*/
if (iter_max) {
iter_max = 300;
while ((tmp & 0x2) && iter_max) {
WREG8(DAC_INDEX, MGA1064_SPAREREG);
tmp = RREG8(DAC_DATA);
udelay(1000);
iter_max--;
}
}
(void)read_poll_timeout(RREG_DAC, tmp, (tmp & 0x2),
1000, 300000, false,
MGA1064_SPAREREG);
}
void mgag200_bmc_start_scanout(struct mga_device *mdev)

6
drivers/gpu/drm/mgag200/mgag200_drv.h
View File

@ -111,6 +111,12 @@
#define DAC_INDEX 0x3c00
#define DAC_DATA 0x3c0a
#define RREG_DAC(reg) \
({ \
WREG8(DAC_INDEX, reg); \
RREG8(DAC_DATA); \
}) \
#define WREG_DAC(reg, v) \
do { \
WREG8(DAC_INDEX, reg); \

2
drivers/gpu/drm/nouveau/include/nvif/client.h
View File

@ -11,7 +11,7 @@ struct nvif_client {
int nvif_client_ctor(struct nvif_client *parent, const char *name, struct nvif_client *);
void nvif_client_dtor(struct nvif_client *);
int nvif_client_suspend(struct nvif_client *);
int nvif_client_suspend(struct nvif_client *, bool);
int nvif_client_resume(struct nvif_client *);
/*XXX*/

2
drivers/gpu/drm/nouveau/include/nvif/driver.h
View File

@ -8,7 +8,7 @@ struct nvif_driver {
const char *name;
int (*init)(const char *name, u64 device, const char *cfg,
const char *dbg, void **priv);
int (*suspend)(void *priv);
int (*suspend)(void *priv, bool runtime);
int (*resume)(void *priv);
int (*ioctl)(void *priv, void *data, u32 size, void **hack);
void __iomem *(*map)(void *priv, u64 handle, u32 size);

3
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View File

@ -2,6 +2,7 @@
#ifndef __NVKM_DEVICE_H__
#define __NVKM_DEVICE_H__
#include <core/oclass.h>
#include <core/suspend_state.h>
#include <core/intr.h>
enum nvkm_subdev_type;
@ -93,7 +94,7 @@ struct nvkm_device_func {
void *(*dtor)(struct nvkm_device *);
int (*preinit)(struct nvkm_device *);
int (*init)(struct nvkm_device *);
void (*fini)(struct nvkm_device *, bool suspend);
void (*fini)(struct nvkm_device *, enum nvkm_suspend_state suspend);
int (*irq)(struct nvkm_device *);
resource_size_t (*resource_addr)(struct nvkm_device *, enum nvkm_bar_id);
resource_size_t (*resource_size)(struct nvkm_device *, enum nvkm_bar_id);

2
drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
View File

@ -20,7 +20,7 @@ struct nvkm_engine_func {
int (*oneinit)(struct nvkm_engine *);
int (*info)(struct nvkm_engine *, u64 mthd, u64 *data);
int (*init)(struct nvkm_engine *);
int (*fini)(struct nvkm_engine *, bool suspend);
int (*fini)(struct nvkm_engine *, enum nvkm_suspend_state suspend);
int (*reset)(struct nvkm_engine *);
int (*nonstall)(struct nvkm_engine *);
void (*intr)(struct nvkm_engine *);

5
drivers/gpu/drm/nouveau/include/nvkm/core/object.h
View File

@ -2,6 +2,7 @@
#ifndef __NVKM_OBJECT_H__
#define __NVKM_OBJECT_H__
#include <core/oclass.h>
#include <core/suspend_state.h>
struct nvkm_event;
struct nvkm_gpuobj;
struct nvkm_uevent;
@ -27,7 +28,7 @@ enum nvkm_object_map {
struct nvkm_object_func {
void *(*dtor)(struct nvkm_object *);
int (*init)(struct nvkm_object *);
int (*fini)(struct nvkm_object *, bool suspend);
int (*fini)(struct nvkm_object *, enum nvkm_suspend_state suspend);
int (*mthd)(struct nvkm_object *, u32 mthd, void *data, u32 size);
int (*ntfy)(struct nvkm_object *, u32 mthd, struct nvkm_event **);
int (*map)(struct nvkm_object *, void *argv, u32 argc,
@ -49,7 +50,7 @@ int nvkm_object_new(const struct nvkm_oclass *, void *data, u32 size,
void nvkm_object_del(struct nvkm_object **);
void *nvkm_object_dtor(struct nvkm_object *);
int nvkm_object_init(struct nvkm_object *);
int nvkm_object_fini(struct nvkm_object *, bool suspend);
int nvkm_object_fini(struct nvkm_object *, enum nvkm_suspend_state);
int nvkm_object_mthd(struct nvkm_object *, u32 mthd, void *data, u32 size);
int nvkm_object_ntfy(struct nvkm_object *, u32 mthd, struct nvkm_event **);
int nvkm_object_map(struct nvkm_object *, void *argv, u32 argc,

2
drivers/gpu/drm/nouveau/include/nvkm/core/oproxy.h
View File

@ -13,7 +13,7 @@ struct nvkm_oproxy {
struct nvkm_oproxy_func {
void (*dtor[2])(struct nvkm_oproxy *);
int (*init[2])(struct nvkm_oproxy *);
int (*fini[2])(struct nvkm_oproxy *, bool suspend);
int (*fini[2])(struct nvkm_oproxy *, enum nvkm_suspend_state suspend);
};
void nvkm_oproxy_ctor(const struct nvkm_oproxy_func *,

4
drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
View File

@ -40,7 +40,7 @@ struct nvkm_subdev_func {
int (*oneinit)(struct nvkm_subdev *);
int (*info)(struct nvkm_subdev *, u64 mthd, u64 *data);
int (*init)(struct nvkm_subdev *);
int (*fini)(struct nvkm_subdev *, bool suspend);
int (*fini)(struct nvkm_subdev *, enum nvkm_suspend_state suspend);
void (*intr)(struct nvkm_subdev *);
};
@ -65,7 +65,7 @@ void nvkm_subdev_unref(struct nvkm_subdev *);
int nvkm_subdev_preinit(struct nvkm_subdev *);
int nvkm_subdev_oneinit(struct nvkm_subdev *);
int nvkm_subdev_init(struct nvkm_subdev *);
int nvkm_subdev_fini(struct nvkm_subdev *, bool suspend);
int nvkm_subdev_fini(struct nvkm_subdev *, enum nvkm_suspend_state suspend);
int nvkm_subdev_info(struct nvkm_subdev *, u64, u64 *);
void nvkm_subdev_intr(struct nvkm_subdev *);

11
drivers/gpu/drm/nouveau/include/nvkm/core/suspend_state.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVKM_SUSPEND_STATE_H__
#define __NVKM_SUSPEND_STATE_H__
enum nvkm_suspend_state {
NVKM_POWEROFF,
NVKM_SUSPEND,
NVKM_RUNTIME_SUSPEND,
};
#endif

6
drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h
View File

@ -44,6 +44,9 @@ typedef void (*nvkm_gsp_event_func)(struct nvkm_gsp_event *, void *repv, u32 rep
* NVKM_GSP_RPC_REPLY_NOWAIT - If specified, immediately return to the
* caller after the GSP RPC command is issued.
*
* NVKM_GSP_RPC_REPLY_NOSEQ - If specified, exactly like NOWAIT
* but don't emit RPC sequence number.
*
* NVKM_GSP_RPC_REPLY_RECV - If specified, wait and receive the entire GSP
* RPC message after the GSP RPC command is issued.
*
@ -53,6 +56,7 @@ typedef void (*nvkm_gsp_event_func)(struct nvkm_gsp_event *, void *repv, u32 rep
*/
enum nvkm_gsp_rpc_reply_policy {
NVKM_GSP_RPC_REPLY_NOWAIT = 0,
NVKM_GSP_RPC_REPLY_NOSEQ,
NVKM_GSP_RPC_REPLY_RECV,
NVKM_GSP_RPC_REPLY_POLL,
};
@ -242,6 +246,8 @@ struct nvkm_gsp {
/* The size of the registry RPC */
size_t registry_rpc_size;
u32 rpc_seq;
#ifdef CONFIG_DEBUG_FS
/*
* Logging buffers in debugfs. The wrapper objects need to remain

2
drivers/gpu/drm/nouveau/nouveau_display.c
View File

@ -352,8 +352,6 @@ nouveau_user_framebuffer_create(struct drm_device *dev,
static const struct drm_mode_config_funcs nouveau_mode_config_funcs = {
.fb_create = nouveau_user_framebuffer_create,
.atomic_commit = drm_atomic_helper_commit,
.atomic_check = drm_atomic_helper_check,
};

2
drivers/gpu/drm/nouveau/nouveau_drm.c
View File

@ -983,7 +983,7 @@ nouveau_do_suspend(struct nouveau_drm *drm, bool runtime)
}
NV_DEBUG(drm, "suspending object tree...\n");
ret = nvif_client_suspend(&drm->_client);
ret = nvif_client_suspend(&drm->_client, runtime);
if (ret)
goto fail_client;

10
drivers/gpu/drm/nouveau/nouveau_nvif.c
View File

@ -62,10 +62,16 @@ nvkm_client_resume(void *priv)
}
static int
nvkm_client_suspend(void *priv)
nvkm_client_suspend(void *priv, bool runtime)
{
struct nvkm_client *client = priv;
return nvkm_object_fini(&client->object, true);
enum nvkm_suspend_state state;
if (runtime)
state = NVKM_RUNTIME_SUSPEND;
else
state = NVKM_SUSPEND;
return nvkm_object_fini(&client->object, state);
}
static int

4
drivers/gpu/drm/nouveau/nvif/client.c
View File

@ -30,9 +30,9 @@
#include <nvif/if0000.h>
int
nvif_client_suspend(struct nvif_client *client)
nvif_client_suspend(struct nvif_client *client, bool runtime)
{
return client->driver->suspend(client->object.priv);
return client->driver->suspend(client->object.priv, runtime);
}
int

4
drivers/gpu/drm/nouveau/nvkm/core/engine.c
View File

@ -41,7 +41,7 @@ nvkm_engine_reset(struct nvkm_engine *engine)
if (engine->func->reset)
return engine->func->reset(engine);
nvkm_subdev_fini(&engine->subdev, false);
nvkm_subdev_fini(&engine->subdev, NVKM_POWEROFF);
return nvkm_subdev_init(&engine->subdev);
}
@ -98,7 +98,7 @@ nvkm_engine_info(struct nvkm_subdev *subdev, u64 mthd, u64 *data)
}
static int
nvkm_engine_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_engine_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
struct nvkm_engine *engine = nvkm_engine(subdev);
if (engine->func->fini)

4
drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
View File

@ -141,7 +141,7 @@ nvkm_ioctl_new(struct nvkm_client *client,
}
ret = -EEXIST;
}
nvkm_object_fini(object, false);
nvkm_object_fini(object, NVKM_POWEROFF);
}
nvkm_object_del(&object);
@ -160,7 +160,7 @@ nvkm_ioctl_del(struct nvkm_client *client,
nvif_ioctl(object, "delete size %d\n", size);
if (!(ret = nvif_unvers(ret, &data, &size, args->none))) {
nvif_ioctl(object, "delete\n");
nvkm_object_fini(object, false);
nvkm_object_fini(object, NVKM_POWEROFF);
nvkm_object_del(&object);
}

20
drivers/gpu/drm/nouveau/nvkm/core/object.c
View File

@ -142,13 +142,25 @@ nvkm_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *gpuobj,
}
int
nvkm_object_fini(struct nvkm_object *object, bool suspend)
nvkm_object_fini(struct nvkm_object *object, enum nvkm_suspend_state suspend)
{
const char *action = suspend ? "suspend" : "fini";
const char *action;
struct nvkm_object *child;
s64 time;
int ret;
switch (suspend) {
case NVKM_POWEROFF:
default:
action = "fini";
break;
case NVKM_SUSPEND:
action = "suspend";
break;
case NVKM_RUNTIME_SUSPEND:
action = "runtime";
break;
}
nvif_debug(object, "%s children...\n", action);
time = ktime_to_us(ktime_get());
list_for_each_entry_reverse(child, &object->tree, head) {
@ -212,11 +224,11 @@ nvkm_object_init(struct nvkm_object *object)
fail_child:
list_for_each_entry_continue_reverse(child, &object->tree, head)
nvkm_object_fini(child, false);
nvkm_object_fini(child, NVKM_POWEROFF);
fail:
nvif_error(object, "init failed with %d\n", ret);
if (object->func->fini)
object->func->fini(object, false);
object->func->fini(object, NVKM_POWEROFF);
return ret;
}

2
drivers/gpu/drm/nouveau/nvkm/core/oproxy.c
View File

@ -87,7 +87,7 @@ nvkm_oproxy_uevent(struct nvkm_object *object, void *argv, u32 argc,
}
static int
nvkm_oproxy_fini(struct nvkm_object *object, bool suspend)
nvkm_oproxy_fini(struct nvkm_object *object, enum nvkm_suspend_state suspend)
{
struct nvkm_oproxy *oproxy = nvkm_oproxy(object);
int ret;

18
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View File

@ -51,12 +51,24 @@ nvkm_subdev_info(struct nvkm_subdev *subdev, u64 mthd, u64 *data)
}
int
nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_subdev_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
struct nvkm_device *device = subdev->device;
const char *action = suspend ? "suspend" : subdev->use.enabled ? "fini" : "reset";
const char *action;
s64 time;
switch (suspend) {
case NVKM_POWEROFF:
default:
action = subdev->use.enabled ? "fini" : "reset";
break;
case NVKM_SUSPEND:
action = "suspend";
break;
case NVKM_RUNTIME_SUSPEND:
action = "runtime";
break;
}
nvkm_trace(subdev, "%s running...\n", action);
time = ktime_to_us(ktime_get());
@ -186,7 +198,7 @@ void
nvkm_subdev_unref(struct nvkm_subdev *subdev)
{
if (refcount_dec_and_mutex_lock(&subdev->use.refcount, &subdev->use.mutex)) {
nvkm_subdev_fini(subdev, false);
nvkm_subdev_fini(subdev, NVKM_POWEROFF);
mutex_unlock(&subdev->use.mutex);
}
}

2
drivers/gpu/drm/nouveau/nvkm/core/uevent.c
View File

@ -73,7 +73,7 @@ nvkm_uevent_mthd(struct nvkm_object *object, u32 mthd, void *argv, u32 argc)
}
static int
nvkm_uevent_fini(struct nvkm_object *object, bool suspend)
nvkm_uevent_fini(struct nvkm_object *object, enum nvkm_suspend_state suspend)
{
struct nvkm_uevent *uevent = nvkm_uevent(object);

2
drivers/gpu/drm/nouveau/nvkm/engine/ce/ga100.c
View File

@ -46,7 +46,7 @@ ga100_ce_nonstall(struct nvkm_engine *engine)
}
int
ga100_ce_fini(struct nvkm_engine *engine, bool suspend)
ga100_ce_fini(struct nvkm_engine *engine, enum nvkm_suspend_state suspend)
{
nvkm_inth_block(&engine->subdev.inth);
return 0;

2
drivers/gpu/drm/nouveau/nvkm/engine/ce/priv.h
View File

@ -14,7 +14,7 @@ extern const struct nvkm_object_func gv100_ce_cclass;
int ga100_ce_oneinit(struct nvkm_engine *);
int ga100_ce_init(struct nvkm_engine *);
int ga100_ce_fini(struct nvkm_engine *, bool);
int ga100_ce_fini(struct nvkm_engine *, enum nvkm_suspend_state);
int ga100_ce_nonstall(struct nvkm_engine *);
u32 gb202_ce_grce_mask(struct nvkm_device *);

22
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -2936,13 +2936,25 @@ nvkm_device_engine(struct nvkm_device *device, int type, int inst)
}
int
nvkm_device_fini(struct nvkm_device *device, bool suspend)
nvkm_device_fini(struct nvkm_device *device, enum nvkm_suspend_state suspend)
{
const char *action = suspend ? "suspend" : "fini";
const char *action;
struct nvkm_subdev *subdev;
int ret;
s64 time;
switch (suspend) {
case NVKM_POWEROFF:
default:
action = "fini";
break;
case NVKM_SUSPEND:
action = "suspend";
break;
case NVKM_RUNTIME_SUSPEND:
action = "runtime";
break;
}
nvdev_trace(device, "%s running...\n", action);
time = ktime_to_us(ktime_get());
@ -3032,7 +3044,7 @@ nvkm_device_init(struct nvkm_device *device)
if (ret)
return ret;
nvkm_device_fini(device, false);
nvkm_device_fini(device, NVKM_POWEROFF);
nvdev_trace(device, "init running...\n");
time = ktime_to_us(ktime_get());
@ -3060,9 +3072,9 @@ nvkm_device_init(struct nvkm_device *device)
fail_subdev:
list_for_each_entry_from(subdev, &device->subdev, head)
nvkm_subdev_fini(subdev, false);
nvkm_subdev_fini(subdev, NVKM_POWEROFF);
fail:
nvkm_device_fini(device, false);
nvkm_device_fini(device, NVKM_POWEROFF);
nvdev_error(device, "init failed with %d\n", ret);
return ret;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c
View File

@ -1605,10 +1605,10 @@ nvkm_device_pci_irq(struct nvkm_device *device)
}
static void
nvkm_device_pci_fini(struct nvkm_device *device, bool suspend)
nvkm_device_pci_fini(struct nvkm_device *device, enum nvkm_suspend_state suspend)
{
struct nvkm_device_pci *pdev = nvkm_device_pci(device);
if (suspend) {
if (suspend != NVKM_POWEROFF) {
pci_disable_device(pdev->pdev);
pdev->suspend = true;
}

2
drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h
View File

@ -56,5 +56,5 @@ int nvkm_device_ctor(const struct nvkm_device_func *,
const char *name, const char *cfg, const char *dbg,
struct nvkm_device *);
int nvkm_device_init(struct nvkm_device *);
int nvkm_device_fini(struct nvkm_device *, bool suspend);
int nvkm_device_fini(struct nvkm_device *, enum nvkm_suspend_state suspend);
#endif

2
drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
View File

@ -218,7 +218,7 @@ nvkm_udevice_map(struct nvkm_object *object, void *argv, u32 argc,
}
static int
nvkm_udevice_fini(struct nvkm_object *object, bool suspend)
nvkm_udevice_fini(struct nvkm_object *object, enum nvkm_suspend_state suspend)
{
struct nvkm_udevice *udev = nvkm_udevice(object);
struct nvkm_device *device = udev->device;

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c
View File

@ -99,13 +99,13 @@ nvkm_disp_intr(struct nvkm_engine *engine)
}
static int
nvkm_disp_fini(struct nvkm_engine *engine, bool suspend)
nvkm_disp_fini(struct nvkm_engine *engine, enum nvkm_suspend_state suspend)
{
struct nvkm_disp *disp = nvkm_disp(engine);
struct nvkm_outp *outp;
if (disp->func->fini)
disp->func->fini(disp, suspend);
disp->func->fini(disp, suspend != NVKM_POWEROFF);
list_for_each_entry(outp, &disp->outps, head) {
if (outp->func->fini)

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.c
View File

@ -128,7 +128,7 @@ nvkm_disp_chan_child_get(struct nvkm_object *object, int index, struct nvkm_ocla
}
static int
nvkm_disp_chan_fini(struct nvkm_object *object, bool suspend)
nvkm_disp_chan_fini(struct nvkm_object *object, enum nvkm_suspend_state suspend)
{
struct nvkm_disp_chan *chan = nvkm_disp_chan(object);

4
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
View File

@ -93,13 +93,13 @@ nvkm_falcon_intr(struct nvkm_engine *engine)
}
static int
nvkm_falcon_fini(struct nvkm_engine *engine, bool suspend)
nvkm_falcon_fini(struct nvkm_engine *engine, enum nvkm_suspend_state suspend)
{
struct nvkm_falcon *falcon = nvkm_falcon(engine);
struct nvkm_device *device = falcon->engine.subdev.device;
const u32 base = falcon->addr;
if (!suspend) {
if (suspend == NVKM_POWEROFF) {
nvkm_memory_unref(&falcon->core);
if (falcon->external) {
vfree(falcon->data.data);

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
View File

@ -122,7 +122,7 @@ nvkm_fifo_class_get(struct nvkm_oclass *oclass, int index, const struct nvkm_dev
}
static int
nvkm_fifo_fini(struct nvkm_engine *engine, bool suspend)
nvkm_fifo_fini(struct nvkm_engine *engine, enum nvkm_suspend_state suspend)
{
struct nvkm_fifo *fifo = nvkm_fifo(engine);
struct nvkm_runl *runl;

6
drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c
View File

@ -72,7 +72,7 @@ struct nvkm_uobj {
};
static int
nvkm_uchan_object_fini_1(struct nvkm_oproxy *oproxy, bool suspend)
nvkm_uchan_object_fini_1(struct nvkm_oproxy *oproxy, enum nvkm_suspend_state suspend)
{
struct nvkm_uobj *uobj = container_of(oproxy, typeof(*uobj), oproxy);
struct nvkm_chan *chan = uobj->chan;
@ -87,7 +87,7 @@ nvkm_uchan_object_fini_1(struct nvkm_oproxy *oproxy, bool suspend)
nvkm_chan_cctx_bind(chan, ectx->engn, NULL);
if (refcount_dec_and_test(&ectx->uses))
nvkm_object_fini(ectx->object, false);
nvkm_object_fini(ectx->object, NVKM_POWEROFF);
mutex_unlock(&chan->cgrp->mutex);
}
@ -269,7 +269,7 @@ nvkm_uchan_map(struct nvkm_object *object, void *argv, u32 argc,
}
static int
nvkm_uchan_fini(struct nvkm_object *object, bool suspend)
nvkm_uchan_fini(struct nvkm_object *object, enum nvkm_suspend_state suspend)
{
struct nvkm_chan *chan = nvkm_uchan(object)->chan;

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c
View File

@ -168,11 +168,11 @@ nvkm_gr_init(struct nvkm_engine *engine)
}
static int
nvkm_gr_fini(struct nvkm_engine *engine, bool suspend)
nvkm_gr_fini(struct nvkm_engine *engine, enum nvkm_suspend_state suspend)
{
struct nvkm_gr *gr = nvkm_gr(engine);
if (gr->func->fini)
return gr->func->fini(gr, suspend);
return gr->func->fini(gr, suspend != NVKM_POWEROFF);
return 0;
}

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View File

@ -2330,7 +2330,7 @@ gf100_gr_reset(struct nvkm_gr *base)
WARN_ON(gf100_gr_fecs_halt_pipeline(gr));
subdev->func->fini(subdev, false);
subdev->func->fini(subdev, NVKM_POWEROFF);
nvkm_mc_disable(device, subdev->type, subdev->inst);
if (gr->func->gpccs.reset)
gr->func->gpccs.reset(gr);

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
View File

@ -1158,7 +1158,7 @@ nv04_gr_chan_dtor(struct nvkm_object *object)
}
static int
nv04_gr_chan_fini(struct nvkm_object *object, bool suspend)
nv04_gr_chan_fini(struct nvkm_object *object, enum nvkm_suspend_state suspend)
{
struct nv04_gr_chan *chan = nv04_gr_chan(object);
struct nv04_gr *gr = chan->gr;

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
View File

@ -951,7 +951,7 @@ nv10_gr_context_switch(struct nv10_gr *gr)
}
static int
nv10_gr_chan_fini(struct nvkm_object *object, bool suspend)
nv10_gr_chan_fini(struct nvkm_object *object, enum nvkm_suspend_state suspend)
{
struct nv10_gr_chan *chan = nv10_gr_chan(object);
struct nv10_gr *gr = chan->gr;

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
View File

@ -27,7 +27,7 @@ nv20_gr_chan_init(struct nvkm_object *object)
}
int
nv20_gr_chan_fini(struct nvkm_object *object, bool suspend)
nv20_gr_chan_fini(struct nvkm_object *object, enum nvkm_suspend_state suspend)
{
struct nv20_gr_chan *chan = nv20_gr_chan(object);
struct nv20_gr *gr = chan->gr;

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
View File

@ -31,5 +31,5 @@ struct nv20_gr_chan {
void *nv20_gr_chan_dtor(struct nvkm_object *);
int nv20_gr_chan_init(struct nvkm_object *);
int nv20_gr_chan_fini(struct nvkm_object *, bool);
int nv20_gr_chan_fini(struct nvkm_object *, enum nvkm_suspend_state);
#endif

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
View File

@ -89,7 +89,7 @@ nv40_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
}
static int
nv40_gr_chan_fini(struct nvkm_object *object, bool suspend)
nv40_gr_chan_fini(struct nvkm_object *object, enum nvkm_suspend_state suspend)
{
struct nv40_gr_chan *chan = nv40_gr_chan(object);
struct nv40_gr *gr = chan->gr;
@ -101,7 +101,7 @@ nv40_gr_chan_fini(struct nvkm_object *object, bool suspend)
nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
if (nvkm_rd32(device, 0x40032c) == inst) {
if (suspend) {
if (suspend != NVKM_POWEROFF) {
nvkm_wr32(device, 0x400720, 0x00000000);
nvkm_wr32(device, 0x400784, inst);
nvkm_mask(device, 0x400310, 0x00000020, 0x00000020);

2
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
View File

@ -65,7 +65,7 @@ nv44_mpeg_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
}
static int
nv44_mpeg_chan_fini(struct nvkm_object *object, bool suspend)
nv44_mpeg_chan_fini(struct nvkm_object *object, enum nvkm_suspend_state suspend)
{
struct nv44_mpeg_chan *chan = nv44_mpeg_chan(object);

2
drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c
View File

@ -37,7 +37,7 @@ nvkm_sec2_finimsg(void *priv, struct nvfw_falcon_msg *hdr)
}
static int
nvkm_sec2_fini(struct nvkm_engine *engine, bool suspend)
nvkm_sec2_fini(struct nvkm_engine *engine, enum nvkm_suspend_state suspend)
{
struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
struct nvkm_subdev *subdev = &sec2->engine.subdev;

4
drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
View File

@ -76,7 +76,7 @@ nvkm_xtensa_intr(struct nvkm_engine *engine)
}
static int
nvkm_xtensa_fini(struct nvkm_engine *engine, bool suspend)
nvkm_xtensa_fini(struct nvkm_engine *engine, enum nvkm_suspend_state suspend)
{
struct nvkm_xtensa *xtensa = nvkm_xtensa(engine);
struct nvkm_device *device = xtensa->engine.subdev.device;
@ -85,7 +85,7 @@ nvkm_xtensa_fini(struct nvkm_engine *engine, bool suspend)
nvkm_wr32(device, base + 0xd84, 0); /* INTR_EN */
nvkm_wr32(device, base + 0xd94, 0); /* FIFO_CTRL */
if (!suspend)
if (suspend == NVKM_POWEROFF)
nvkm_memory_unref(&xtensa->gpu_fw);
return 0;
}

2
drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c
View File

@ -182,7 +182,7 @@ nvkm_acr_managed_falcon(struct nvkm_device *device, enum nvkm_acr_lsf_id id)
}
static int
nvkm_acr_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_acr_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
if (!subdev->use.enabled)
return 0;

2
drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
View File

@ -90,7 +90,7 @@ nvkm_bar_bar2_init(struct nvkm_device *device)
}
static int
nvkm_bar_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_bar_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
struct nvkm_bar *bar = nvkm_bar(subdev);

2
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
View File

@ -577,7 +577,7 @@ nvkm_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
}
static int
nvkm_clk_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_clk_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
struct nvkm_clk *clk = nvkm_clk(subdev);
flush_work(&clk->work);

4
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c
View File

@ -67,11 +67,11 @@ nvkm_devinit_post(struct nvkm_devinit *init)
}
static int
nvkm_devinit_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_devinit_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
struct nvkm_devinit *init = nvkm_devinit(subdev);
/* force full reinit on resume */
if (suspend)
if (suspend != NVKM_POWEROFF)
init->post = true;
return 0;
}

2
drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c
View File

@ -51,7 +51,7 @@ nvkm_fault_intr(struct nvkm_subdev *subdev)
}
static int
nvkm_fault_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_fault_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
struct nvkm_fault *fault = nvkm_fault(subdev);
if (fault->func->fini)

2
drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.c
View File

@ -56,7 +56,7 @@ nvkm_ufault_map(struct nvkm_object *object, void *argv, u32 argc,
}
static int
nvkm_ufault_fini(struct nvkm_object *object, bool suspend)
nvkm_ufault_fini(struct nvkm_object *object, enum nvkm_suspend_state suspend)
{
struct nvkm_fault_buffer *buffer = nvkm_fault_buffer(object);
buffer->fault->func->buffer.fini(buffer);

2
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
View File

@ -144,7 +144,7 @@ nvkm_gpio_intr(struct nvkm_subdev *subdev)
}
static int
nvkm_gpio_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_gpio_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
struct nvkm_gpio *gpio = nvkm_gpio(subdev);
u32 mask = (1ULL << gpio->func->lines) - 1;

2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c
View File

@ -48,7 +48,7 @@ nvkm_gsp_intr_stall(struct nvkm_gsp *gsp, enum nvkm_subdev_type type, int inst)
}
static int
nvkm_gsp_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_gsp_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
struct nvkm_gsp *gsp = nvkm_gsp(subdev);

2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gh100.c
View File

@ -17,7 +17,7 @@
#include <nvhw/ref/gh100/dev_riscv_pri.h>
int
gh100_gsp_fini(struct nvkm_gsp *gsp, bool suspend)
gh100_gsp_fini(struct nvkm_gsp *gsp, enum nvkm_suspend_state suspend)
{
struct nvkm_falcon *falcon = &gsp->falcon;
int ret, time = 4000;

8
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/priv.h
View File

@ -59,7 +59,7 @@ struct nvkm_gsp_func {
void (*dtor)(struct nvkm_gsp *);
int (*oneinit)(struct nvkm_gsp *);
int (*init)(struct nvkm_gsp *);
int (*fini)(struct nvkm_gsp *, bool suspend);
int (*fini)(struct nvkm_gsp *, enum nvkm_suspend_state suspend);
int (*reset)(struct nvkm_gsp *);
struct {
@ -75,7 +75,7 @@ int tu102_gsp_fwsec_sb_ctor(struct nvkm_gsp *);
void tu102_gsp_fwsec_sb_dtor(struct nvkm_gsp *);
int tu102_gsp_oneinit(struct nvkm_gsp *);
int tu102_gsp_init(struct nvkm_gsp *);
int tu102_gsp_fini(struct nvkm_gsp *, bool suspend);
int tu102_gsp_fini(struct nvkm_gsp *, enum nvkm_suspend_state suspend);
int tu102_gsp_reset(struct nvkm_gsp *);
u64 tu102_gsp_wpr_heap_size(struct nvkm_gsp *);
@ -87,12 +87,12 @@ int ga102_gsp_reset(struct nvkm_gsp *);
int gh100_gsp_oneinit(struct nvkm_gsp *);
int gh100_gsp_init(struct nvkm_gsp *);
int gh100_gsp_fini(struct nvkm_gsp *, bool suspend);
int gh100_gsp_fini(struct nvkm_gsp *, enum nvkm_suspend_state suspend);
void r535_gsp_dtor(struct nvkm_gsp *);
int r535_gsp_oneinit(struct nvkm_gsp *);
int r535_gsp_init(struct nvkm_gsp *);
int r535_gsp_fini(struct nvkm_gsp *, bool suspend);
int r535_gsp_fini(struct nvkm_gsp *, enum nvkm_suspend_state suspend);
int nvkm_gsp_new_(const struct nvkm_gsp_fwif *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_gsp **);

2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fbsr.c
View File

@ -208,7 +208,7 @@ r535_fbsr_resume(struct nvkm_gsp *gsp)
}
static int
r535_fbsr_suspend(struct nvkm_gsp *gsp)
r535_fbsr_suspend(struct nvkm_gsp *gsp, bool runtime)
{
struct nvkm_subdev *subdev = &gsp->subdev;
struct nvkm_device *device = subdev->device;

8
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
View File

@ -704,7 +704,7 @@ r535_gsp_rpc_set_registry(struct nvkm_gsp *gsp)
build_registry(gsp, rpc);
return nvkm_gsp_rpc_wr(gsp, rpc, NVKM_GSP_RPC_REPLY_NOWAIT);
return nvkm_gsp_rpc_wr(gsp, rpc, NVKM_GSP_RPC_REPLY_NOSEQ);
fail:
clean_registry(gsp);
@ -921,7 +921,7 @@ r535_gsp_set_system_info(struct nvkm_gsp *gsp)
info->pciConfigMirrorSize = device->pci->func->cfg.size;
r535_gsp_acpi_info(gsp, &info->acpiMethodData);
return nvkm_gsp_rpc_wr(gsp, info, NVKM_GSP_RPC_REPLY_NOWAIT);
return nvkm_gsp_rpc_wr(gsp, info, NVKM_GSP_RPC_REPLY_NOSEQ);
}
static int
@ -1721,7 +1721,7 @@ r535_gsp_sr_data_size(struct nvkm_gsp *gsp)
}
int
r535_gsp_fini(struct nvkm_gsp *gsp, bool suspend)
r535_gsp_fini(struct nvkm_gsp *gsp, enum nvkm_suspend_state suspend)
{
struct nvkm_rm *rm = gsp->rm;
int ret;
@ -1748,7 +1748,7 @@ r535_gsp_fini(struct nvkm_gsp *gsp, bool suspend)
sr->sysmemAddrOfSuspendResumeData = gsp->sr.radix3.lvl0.addr;
sr->sizeOfSuspendResumeData = len;
ret = rm->api->fbsr->suspend(gsp);
ret = rm->api->fbsr->suspend(gsp, suspend == NVKM_RUNTIME_SUSPEND);
if (ret) {
nvkm_gsp_mem_dtor(&gsp->sr.meta);
nvkm_gsp_radix3_dtor(gsp, &gsp->sr.radix3);

6
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rpc.c
View File

@ -557,6 +557,7 @@ r535_gsp_rpc_handle_reply(struct nvkm_gsp *gsp, u32 fn,
switch (policy) {
case NVKM_GSP_RPC_REPLY_NOWAIT:
case NVKM_GSP_RPC_REPLY_NOSEQ:
break;
case NVKM_GSP_RPC_REPLY_RECV:
reply = r535_gsp_msg_recv(gsp, fn, gsp_rpc_len);
@ -588,6 +589,11 @@ r535_gsp_rpc_send(struct nvkm_gsp *gsp, void *payload,
rpc->data, rpc->length - sizeof(*rpc), true);
}
if (policy == NVKM_GSP_RPC_REPLY_NOSEQ)
rpc->sequence = 0;
else
rpc->sequence = gsp->rpc_seq++;
ret = r535_gsp_cmdq_push(gsp, rpc);
if (ret)
return ERR_PTR(ret);

8
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fbsr.c
View File

@ -62,7 +62,7 @@ r570_fbsr_resume(struct nvkm_gsp *gsp)
}
static int
r570_fbsr_init(struct nvkm_gsp *gsp, struct sg_table *sgt, u64 size)
r570_fbsr_init(struct nvkm_gsp *gsp, struct sg_table *sgt, u64 size, bool runtime)
{
NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS *ctrl;
struct nvkm_gsp_object memlist;
@ -81,7 +81,7 @@ r570_fbsr_init(struct nvkm_gsp *gsp, struct sg_table *sgt, u64 size)
ctrl->hClient = gsp->internal.client.object.handle;
ctrl->hSysMem = memlist.handle;
ctrl->sysmemAddrOfSuspendResumeData = gsp->sr.meta.addr;
ctrl->bEnteringGcoffState = 1;
ctrl->bEnteringGcoffState = runtime ? 1 : 0;
ret = nvkm_gsp_rm_ctrl_wr(&gsp->internal.device.subdevice, ctrl);
if (ret)
@ -92,7 +92,7 @@ r570_fbsr_init(struct nvkm_gsp *gsp, struct sg_table *sgt, u64 size)
}
static int
r570_fbsr_suspend(struct nvkm_gsp *gsp)
r570_fbsr_suspend(struct nvkm_gsp *gsp, bool runtime)
{
struct nvkm_subdev *subdev = &gsp->subdev;
struct nvkm_device *device = subdev->device;
@ -133,7 +133,7 @@ r570_fbsr_suspend(struct nvkm_gsp *gsp)
return ret;
/* Initialise FBSR on RM. */
ret = r570_fbsr_init(gsp, &gsp->sr.fbsr, size);
ret = r570_fbsr_init(gsp, &gsp->sr.fbsr, size, runtime);
if (ret) {
nvkm_gsp_sg_free(device, &gsp->sr.fbsr);
return ret;

2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gsp.c
View File

@ -176,7 +176,7 @@ r570_gsp_set_system_info(struct nvkm_gsp *gsp)
info->bIsPrimary = video_is_primary_device(device->dev);
info->bPreserveVideoMemoryAllocations = false;
return nvkm_gsp_rpc_wr(gsp, info, NVKM_GSP_RPC_REPLY_NOWAIT);
return nvkm_gsp_rpc_wr(gsp, info, NVKM_GSP_RPC_REPLY_NOSEQ);
}
static void

2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h
View File

@ -78,7 +78,7 @@ struct nvkm_rm_api {
} *device;
const struct nvkm_rm_api_fbsr {
int (*suspend)(struct nvkm_gsp *);
int (*suspend)(struct nvkm_gsp *, bool runtime);
void (*resume)(struct nvkm_gsp *);
} *fbsr;

2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c
View File

@ -161,7 +161,7 @@ tu102_gsp_reset(struct nvkm_gsp *gsp)
}
int
tu102_gsp_fini(struct nvkm_gsp *gsp, bool suspend)
tu102_gsp_fini(struct nvkm_gsp *gsp, enum nvkm_suspend_state suspend)
{
u32 mbox0 = 0xff, mbox1 = 0xff;
int ret;

2
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
View File

@ -135,7 +135,7 @@ nvkm_i2c_intr(struct nvkm_subdev *subdev)
}
static int
nvkm_i2c_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_i2c_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
struct nvkm_i2c *i2c = nvkm_i2c(subdev);
struct nvkm_i2c_pad *pad;

2
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
View File

@ -176,7 +176,7 @@ nvkm_instmem_boot(struct nvkm_instmem *imem)
}
static int
nvkm_instmem_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_instmem_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
struct nvkm_instmem *imem = nvkm_instmem(subdev);
int ret;

2
drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c
View File

@ -74,7 +74,7 @@ nvkm_pci_rom_shadow(struct nvkm_pci *pci, bool shadow)
}
static int
nvkm_pci_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_pci_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
struct nvkm_pci *pci = nvkm_pci(subdev);

2
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c
View File

@ -77,7 +77,7 @@ nvkm_pmu_intr(struct nvkm_subdev *subdev)
}
static int
nvkm_pmu_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_pmu_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
struct nvkm_pmu *pmu = nvkm_pmu(subdev);

6
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
View File

@ -341,15 +341,15 @@ nvkm_therm_intr(struct nvkm_subdev *subdev)
}
static int
nvkm_therm_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_therm_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
struct nvkm_therm *therm = nvkm_therm(subdev);
if (therm->func->fini)
therm->func->fini(therm);
nvkm_therm_fan_fini(therm, suspend);
nvkm_therm_sensor_fini(therm, suspend);
nvkm_therm_fan_fini(therm, suspend != NVKM_POWEROFF);
nvkm_therm_sensor_fini(therm, suspend != NVKM_POWEROFF);
if (suspend) {
therm->suspend = therm->mode;

2
drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c
View File

@ -149,7 +149,7 @@ nvkm_timer_intr(struct nvkm_subdev *subdev)
}
static int
nvkm_timer_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_timer_fini(struct nvkm_subdev *subdev, enum nvkm_suspend_state suspend)
{
struct nvkm_timer *tmr = nvkm_timer(subdev);
tmr->func->alarm_fini(tmr);

6
drivers/gpu/drm/xe/xe_guc.c
View File

@ -1618,7 +1618,7 @@ int xe_guc_start(struct xe_guc *guc)
return xe_guc_submit_start(guc);
}
void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
int xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
{
struct xe_gt *gt = guc_to_gt(guc);
unsigned int fw_ref;
@ -1630,7 +1630,7 @@ void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
if (!IS_SRIOV_VF(gt_to_xe(gt))) {
fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
if (!fw_ref)
return;
return -EIO;
status = xe_mmio_read32(&gt->mmio, GUC_STATUS);
@ -1658,6 +1658,8 @@ void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
drm_puts(p, "\n");
xe_guc_submit_print(guc, p);
return 0;
}
/**

2
drivers/gpu/drm/xe/xe_guc.h
View File

@ -45,7 +45,7 @@ int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val);
int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val);
void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir);
void xe_guc_sanitize(struct xe_guc *guc);
void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p);
int xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p);
int xe_guc_reset_prepare(struct xe_guc *guc);
void xe_guc_reset_wait(struct xe_guc *guc);
void xe_guc_stop_prepare(struct xe_guc *guc);

2
drivers/gpu/drm/xe/xe_migrate.c
View File

@ -1201,7 +1201,7 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
}
/**
* xe_get_migrate_exec_queue() - Get the execution queue from migrate context.
* xe_migrate_exec_queue() - Get the execution queue from migrate context.
* @migrate: Migrate context.
*
* Return: Pointer to execution queue on success, error on failure

13
drivers/gpu/drm/xe/xe_pm.c
View File

@ -8,6 +8,7 @@
#include <linux/fault-inject.h>
#include <linux/pm_runtime.h>
#include <linux/suspend.h>
#include <linux/dmi.h>
#include <drm/drm_managed.h>
#include <drm/ttm/ttm_placement.h>
@ -357,9 +358,15 @@ ALLOW_ERROR_INJECTION(xe_pm_init_early, ERRNO); /* See xe_pci_probe() */
static u32 vram_threshold_value(struct xe_device *xe)
{
/* FIXME: D3Cold temporarily disabled by default on BMG */
if (xe->info.platform == XE_BATTLEMAGE)
return 0;
if (xe->info.platform == XE_BATTLEMAGE) {
const char *product_name;
product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
if (product_name && strstr(product_name, "NUC13RNG")) {
drm_warn(&xe->drm, "BMG + D3Cold not supported on this platform\n");
return 0;
}
}
return DEFAULT_VRAM_THRESHOLD;
}

2
drivers/gpu/drm/xe/xe_query.c
View File

@ -491,7 +491,7 @@ static int copy_mask(void __user **ptr,
if (copy_to_user(*ptr, topo, sizeof(*topo)))
return -EFAULT;
*ptr += sizeof(topo);
*ptr += sizeof(*topo);
if (copy_to_user(*ptr, mask, mask_size))
return -EFAULT;

2
drivers/gpu/drm/xe/xe_tlb_inval.c
View File

@ -115,7 +115,7 @@ static void tlb_inval_fini(struct drm_device *drm, void *arg)
}
/**
* xe_gt_tlb_inval_init - Initialize TLB invalidation state
* xe_gt_tlb_inval_init_early() - Initialize TLB invalidation state
* @gt: GT structure
*
* Initialize TLB invalidation state, purely software initialization, should

2
drivers/gpu/drm/xe/xe_tlb_inval_job.c
View File

@ -164,7 +164,7 @@ static void xe_tlb_inval_job_destroy(struct kref *ref)
}
/**
* xe_tlb_inval_alloc_dep() - TLB invalidation job alloc dependency
* xe_tlb_inval_job_alloc_dep() - TLB invalidation job alloc dependency
* @job: TLB invalidation job to alloc dependency for
*
* Allocate storage for a dependency in the TLB invalidation fence. This