github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-30 18:13:41 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader

Browse Source 
Add bootph-pre-ram hinting to jh7110.dtsi:
  - CPU interrupt controller(s)
  - gmac1_rgmii_rxin fixed-clock (dependency of syscrg)
  - gmac1_rmii_refin fixed-clock (dependency of syscrg)
  - oscillator
  - core local interrupt timer
  - syscrg clock-controller
  - pllclk clock-controller (dependency of syscrg)
  - DDR memory controller

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
E Shattow 2025-08-23 03:01:43 -07:00 committed by Conor Dooley
parent 7114969021
commit 8181cc2f3f
1 changed files with 12 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/riscv/boot/dts/starfive/jh7110.dtsi
View File

@ -35,6 +35,7 @@ S7_0: cpu@0 {
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
@ -68,6 +69,7 @@ U74_1: cpu@1 {
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
@ -101,6 +103,7 @@ U74_2: cpu@2 {
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
@ -134,6 +137,7 @@ U74_3: cpu@3 {
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
@ -167,6 +171,7 @@ U74_4: cpu@4 {
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
bootph-pre-ram;
interrupt-controller;
#interrupt-cells = <1>;
};
@ -273,12 +278,14 @@ gmac0_rmii_refin: gmac0-rmii-refin-clock {
gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
compatible = "fixed-clock";
bootph-pre-ram;
clock-output-names = "gmac1_rgmii_rxin";
#clock-cells = <0>;
};
gmac1_rmii_refin: gmac1-rmii-refin-clock {
compatible = "fixed-clock";
bootph-pre-ram;
clock-output-names = "gmac1_rmii_refin";
#clock-cells = <0>;
};
@ -321,6 +328,7 @@ mclk_ext: mclk-ext-clock {
osc: oscillator {
compatible = "fixed-clock";
bootph-pre-ram;
clock-output-names = "osc";
#clock-cells = <0>;
};
@ -354,6 +362,7 @@ soc {
clint: timer@2000000 {
compatible = "starfive,jh7110-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
bootph-pre-ram;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>,
<&cpu2_intc 3>, <&cpu2_intc 7>,
@ -880,6 +889,7 @@ qspi: spi@13010000 {
syscrg: clock-controller@13020000 {
compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;
bootph-pre-ram;
clocks = <&osc>, <&gmac1_rmii_refin>,
<&gmac1_rgmii_rxin>,
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
@ -904,6 +914,7 @@ sys_syscon: syscon@13030000 {
pllclk: clock-controller {
compatible = "starfive,jh7110-pll";
bootph-pre-ram;
clocks = <&osc>;
#clock-cells = <1>;
};
@ -935,6 +946,7 @@ memory-controller@15700000 {
compatible = "starfive,jh7110-dmc";
reg = <0x0 0x15700000 0x0 0x10000>,
<0x0 0x13000000 0x0 0x10000>;
bootph-pre-ram;
clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
clock-names = "pll";
resets = <&syscrg JH7110_SYSRST_DDR_AXI>,