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dt-bindings: riscv: cpus: Fix yamllint style issues

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Wrap an overlong description line and normalize the inline dependency
lists to satisfy yamllint.

Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260824-ultrarisc-dts-v1-1-61ab7aebe9e5@ultrarisc.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
This commit is contained in:
Jia Wang 2026-08-24 13:54:14 +08:00 committed by Paul Walmsley
parent 93a27367ba
commit 817ecd588f
1 changed files with 4 additions and 4 deletions
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8
Documentation/devicetree/bindings/riscv/cpus.yaml
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@ -117,8 +117,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
description:
VLEN/8, the vector register length in bytes. This property is required on
thead systems where the vector register length is not identical on all harts, or
the vlenb CSR is not available.
thead systems where the vector register length is not identical on all
harts, or the vlenb CSR is not available.
# RISC-V has multiple properties for cache op block sizes as the sizes
# differ between individual CBO extensions
@ -151,8 +151,8 @@ anyOf:
- riscv,isa-base
dependencies:
riscv,isa-base: [ "riscv,isa-extensions" ]
riscv,isa-extensions: [ "riscv,isa-base" ]
riscv,isa-base: ["riscv,isa-extensions"]
riscv,isa-extensions: ["riscv,isa-base"]
required:
- interrupt-controller