github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-03 20:14:06 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

ARM: tegra: Device tree changes for v5.13-rc1

Browse Source 
This contains a couple of improvements and fixes for various 32-bit
 Tegra-based boards.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmBl/sITHHRyZWRpbmdA
 bnZpZGlhLmNvbQAKCRDdI6zXfz6zoeC/EAClvdda6xOMJjN/A1MNHc9uMjO8g9hb
 nDdg0mL2nSeTngP+S2hQI177483S/7znFcDIbB1CXsUU67Agy1E5BdPrKHrNkXdw
 0eNJVOUJMhMBjjo2TVqrPRVZkrsww7xWVUzPFMcI+b9Y90R0luGlv8Y3VVn5fvst
 d0orUfi+HxyYFEQGdOeJuiCaIFLVEubOpc1XUuaQTeNbz0zIWYPFRyXYk8VrebG2
 4LnTgTI5YE6K/cJQDI9wfPhf7jREQHRFgf9ejV424FV06cp8JvdeA4ooUtffVb46
 jk8lGUlILLuZ6SiRgcCYuSu3B06OZGrbDupBsfgapOURNPLmfUk3wB7ZuxOtc1qx
 rCQvOaHKLnewaMoSosRXPk0FSykm41aMB5yIZ1H0OQux3UfORjGce3cneeqYppkB
 FY4nBcfeQBzhwqUowugUkDRgTVrB8Z69wtjf9f35jSCE+8oOK0JTCHvalxgf9uk1
 GQc3IE4eKRN986gNrCm4uNdrOKc17pFNQsc5CazJko8xSd2AAcwszV0vj3M1zMkD
 COkXsQ9DppZZ9wZJIZ5assRAyt8/dhUa5elhAXmcq3t5p56bKkTWR1O69ct1gn1n
 2xRBkhqDOowgMD0qYdAxGjTmfho7EEgtH+VaDqtkP3Q7v23IQptNqYJFw9VoZBdu
 oA/3+xqblT7soA==
 =TBic
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-5.13-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

ARM: tegra: Device tree changes for v5.13-rc1

This contains a couple of improvements and fixes for various 32-bit
Tegra-based boards.

* tag 'tegra-for-5.13-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: acer-a500: Add atmel,wakeup-method property
  ARM: tegra: Specify tps65911 as wakeup source
  ARM: tegra: Specify memory suspend OPP in device-tree
  ARM: tegra: Specify CPU suspend OPP in device-tree
  ARM: tegra: ouya: Specify all CPU cores as cooling devices
  ARM: tegra: nexus7: Specify all CPU cores as cooling devices
  ARM: tegra: acer-a500: Rename avdd to vdda of touchscreen node
  ARM: tegra: acer-a500: Specify all CPU cores as cooling devices
  ARM: tegra: acer-a500: Reduce thermal throttling hysteresis to 0.2C
  ARM: tegra: acer-a500: Enable core voltage scaling
  ARM: tegra: paz00: Enable full voltage scaling ranges for CPU and Core domains
  ARM: tegra: cardhu: Support CPU thermal throttling
  ARM: tegra: cardhu: Support CPU frequency and voltage scaling on all board variants
  ARM: tegra: ventana: Support CPU thermal throttling
  ARM: tegra: ventana: Support CPU and Core voltage scaling

Link: https://lore.kernel.org/r/20210401172622.3352990-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2021-04-01 22:01:53 +02:00
commit 815bacb522
16 changed files with 204 additions and 84 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/boot/dts/tegra124-peripherals-opp.dtsi
View File

@ -128,24 +128,28 @@ opp@204000000,800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0003>;
opp-suspend;
};
opp@204000000,950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0008>;
opp-suspend;
};
opp@204000000,1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0010>;
opp-suspend;
};
opp@204000000,1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0004>;
opp-suspend;
};
opp@264000000,800 {
@ -360,6 +364,7 @@ opp@204000000 {
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <3264000>;
opp-suspend;
};
opp@264000000 {

16
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
View File

@ -448,8 +448,10 @@ touchscreen@4c {
reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
avdd-supply = <&vdd_3v3_sys>;
vdda-supply = <&vdd_3v3_sys>;
vdd-supply = <&vdd_3v3_sys>;
atmel,wakeup-method = <1>;
};
gyroscope@68 {
@ -575,7 +577,7 @@ sys_reg: sys {
vdd_core: sm0 {
regulator-name = "vdd_sm0,vdd_core";
regulator-min-microvolt = <1200000>;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1300000>;
regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
regulator-coupled-max-spread = <170000 550000>;
@ -616,7 +618,7 @@ ldo1 {
rtc_vdd: ldo2 {
regulator-name = "vdd_ldo2,vdd_rtc";
regulator-min-microvolt = <1200000>;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1300000>;
regulator-coupled-with = <&vdd_core &vdd_cpu>;
regulator-coupled-max-spread = <170000 550000>;
@ -838,9 +840,10 @@ cpu0: cpu@0 {
#cooling-cells = <2>;
};
cpu@1 {
cpu1: cpu@1 {
cpu-supply = <&vdd_cpu>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
};
@ -1055,7 +1058,7 @@ trips {
trip0: cpu-alert0 {
/* start throttling at 50C */
temperature = <50000>;
hysteresis = <3000>;
hysteresis = <200>;
type = "passive";
};
@ -1070,7 +1073,8 @@ trip1: cpu-crit {
cooling-maps {
map0 {
trip = <&trip0>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

2
arch/arm/boot/dts/tegra20-cpu-opp.dtsi
View File

@ -9,12 +9,14 @@ opp@216000000,750 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x0F 0x0003>;
opp-hz = /bits/ 64 <216000000>;
opp-suspend;
};
opp@216000000,800 {
clock-latency-ns = <400000>;
opp-supported-hw = <0x0F 0x0004>;
opp-hz = /bits/ 64 <216000000>;
opp-suspend;
};
opp@312000000,750 {

14
arch/arm/boot/dts/tegra20-paz00.dts
View File

@ -387,10 +387,10 @@ sys_reg: sys {
core_vdd_reg: sm0 {
regulator-name = "+1.2vs_sm0,vdd_core";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1225000>;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1300000>;
regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>;
regulator-coupled-max-spread = <170000 450000>;
regulator-coupled-max-spread = <170000 550000>;
regulator-always-on;
nvidia,tegra-core-regulator;
@ -401,7 +401,7 @@ cpu_vdd_reg: sm1 {
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1100000>;
regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>;
regulator-coupled-max-spread = <450000 450000>;
regulator-coupled-max-spread = <550000 550000>;
regulator-always-on;
nvidia,tegra-cpu-regulator;
@ -425,10 +425,10 @@ ldo1 {
rtc_vdd_reg: ldo2 {
regulator-name = "+1.2vs_ldo2,vdd_rtc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1225000>;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1300000>;
regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>;
regulator-coupled-max-spread = <170000 450000>;
regulator-coupled-max-spread = <170000 550000>;
regulator-always-on;
nvidia,tegra-rtc-regulator;

1
arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
View File

@ -68,6 +68,7 @@ opp@216000000 {
opp-microvolt = <1000000 1000000 1300000>;
opp-hz = /bits/ 64 <216000000>;
opp-supported-hw = <0x000F>;
opp-suspend;
};
opp@300000000 {

78
arch/arm/boot/dts/tegra20-ventana.dts
View File

@ -2,8 +2,10 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/thermal/thermal.h>
#include "tegra20.dtsi"
#include "tegra20-cpu-opp.dtsi"
#include "tegra20-cpu-opp-microvolt.dtsi"
/ {
model = "NVIDIA Tegra20 Ventana evaluation board";
@ -420,18 +422,28 @@ sys_reg: sys {
regulator-always-on;
};
sm0 {
vdd_core: sm0 {
regulator-name = "vdd_sm0,vdd_core";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1300000>;
regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
regulator-coupled-max-spread = <170000 550000>;
regulator-always-on;
regulator-boot-on;
nvidia,tegra-core-regulator;
};
sm1 {
vdd_cpu: sm1 {
regulator-name = "vdd_sm1,vdd_cpu";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1125000>;
regulator-coupled-with = <&vdd_core &rtc_vdd>;
regulator-coupled-max-spread = <550000 550000>;
regulator-always-on;
regulator-boot-on;
nvidia,tegra-cpu-regulator;
};
sm2_reg: sm2 {
@ -450,10 +462,16 @@ ldo1 {
regulator-always-on;
};
ldo2 {
rtc_vdd: ldo2 {
regulator-name = "vdd_ldo2,vdd_rtc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1300000>;
regulator-coupled-with = <&vdd_core &vdd_cpu>;
regulator-coupled-max-spread = <170000 550000>;
regulator-always-on;
regulator-boot-on;
nvidia,tegra-rtc-regulator;
};
ldo3 {
@ -511,9 +529,10 @@ ldo_rtc {
};
};
temperature-sensor@4c {
nct1008: temperature-sensor@4c {
compatible = "onnn,nct1008";
reg = <0x4c>;
#thermal-sensor-cells = <1>;
};
};
@ -595,11 +614,15 @@ clk32k_in: clock@0 {
cpus {
cpu0: cpu@0 {
cpu-supply = <&vdd_cpu>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
cpu@1 {
cpu1: cpu@1 {
cpu-supply = <&vdd_cpu>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
};
@ -697,4 +720,37 @@ sound {
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <1000>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
thermal-sensors = <&nct1008 1>;
trips {
trip0: cpu-alert0 {
/* start throttling at 50C */
temperature = <50000>;
hysteresis = <200>;
type = "passive";
};
trip1: cpu-crit {
/* shut down at 60C */
temperature = <60000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&trip0>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
};

1
arch/arm/boot/dts/tegra30-apalis.dtsi
View File

@ -860,6 +860,7 @@ pmic: pmic@2d {
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
wakeup-source;
ti,system-power-controller;

14
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
View File

@ -1056,19 +1056,22 @@ cpu0: cpu@0 {
#cooling-cells = <2>;
};
cpu@1 {
cpu1: cpu@1 {
cpu-supply = <&vdd_cpu>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
cpu@2 {
cpu2: cpu@2 {
cpu-supply = <&vdd_cpu>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
cpu@3 {
cpu3: cpu@3 {
cpu-supply = <&vdd_cpu>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
};
@ -1281,7 +1284,10 @@ trip1: cpu-crit {
cooling-maps {
map0 {
trip = <&trip0>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

1
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi
View File

@ -12,6 +12,7 @@ pmic: pmic@2d {
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
wakeup-source;
ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
ti,system-power-controller;

1
arch/arm/boot/dts/tegra30-beaver.dts
View File

@ -1776,6 +1776,7 @@ pmic: tps65911@2d {
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
wakeup-source;
ti,system-power-controller;

48
arch/arm/boot/dts/tegra30-cardhu-a04.dts
View File

@ -2,8 +2,6 @@
/dts-v1/;
#include "tegra30-cardhu.dtsi"
#include "tegra30-cpu-opp.dtsi"
#include "tegra30-cpu-opp-microvolt.dtsi"
/* This dts file support the cardhu A04 and later versions of board */
@ -92,50 +90,4 @@ vdd_bl2_reg: regulator@106 {
enable-active-high;
gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
};
i2c@7000d000 {
pmic: tps65911@2d {
regulators {
vddctrl_reg: vddctrl {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1125000>;
regulator-coupled-with = <&vddcore_reg>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
nvidia,tegra-cpu-regulator;
};
};
};
vddcore_reg: tps62361@60 {
regulator-coupled-with = <&vddctrl_reg>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
nvidia,tegra-core-regulator;
};
};
cpus {
cpu0: cpu@0 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@1 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@2 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@3 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
};
};

84
arch/arm/boot/dts/tegra30-cardhu.dtsi
View File

@ -1,6 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
#include <dt-bindings/thermal/thermal.h>
#include "tegra30.dtsi"
#include "tegra30-cpu-opp.dtsi"
#include "tegra30-cpu-opp-microvolt.dtsi"
/**
* This file contains common DT entry for all fab version of Cardhu.
@ -240,6 +243,7 @@ pmic: tps65911@2d {
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
wakeup-source;
ti,system-power-controller;
@ -272,9 +276,14 @@ vdd2_reg: vdd2 {
vddctrl_reg: vddctrl {
regulator-name = "vdd_cpu,vdd_sys";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
regulator-coupled-with = <&vdd_core>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
regulator-always-on;
nvidia,tegra-cpu-regulator;
};
vio_reg: vio {
@ -334,25 +343,31 @@ ldo8_reg: ldo8 {
};
};
temperature-sensor@4c {
nct1008: temperature-sensor@4c {
compatible = "onnn,nct1008";
reg = <0x4c>;
vcc-supply = <&sys_3v3_reg>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
#thermal-sensor-cells = <1>;
};
tps62361@60 {
vdd_core: tps62361@60 {
compatible = "ti,tps62361";
reg = <0x60>;
regulator-name = "tps62361-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1500000>;
regulator-coupled-with = <&vddctrl_reg>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
regulator-boot-on;
regulator-always-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
nvidia,tegra-core-regulator;
};
};
@ -424,6 +439,32 @@ clk32k_in: clock@0 {
#clock-cells = <0>;
};
cpus {
cpu0: cpu@0 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
cpu2: cpu@2 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
cpu3: cpu@3 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
};
panel: panel {
compatible = "chunghwa,claa101wb01";
ddc-i2c-bus = <&panelddc>;
@ -603,6 +644,41 @@ sound {
<&tegra_car TEGRA30_CLK_EXTERN1>;
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <1000>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
thermal-sensors = <&nct1008 1>;
trips {
trip0: cpu-alert0 {
/* throttle at 57C until temperature drops to 56.8C */
temperature = <57000>;
hysteresis = <200>;
type = "passive";
};
trip1: cpu-crit {
/* shut down at 60C */
temperature = <60000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&trip0>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";

1
arch/arm/boot/dts/tegra30-colibri.dtsi
View File

@ -737,6 +737,7 @@ pmic: pmic@2d {
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
wakeup-source;
ti,system-power-controller;

3
arch/arm/boot/dts/tegra30-cpu-opp.dtsi
View File

@ -45,18 +45,21 @@ opp@204000000,800 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x31FE>;
opp-hz = /bits/ 64 <204000000>;
opp-suspend;
};
opp@204000000,850 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0C01>;
opp-hz = /bits/ 64 <204000000>;
opp-suspend;
};
opp@204000000,912 {
clock-latency-ns = <100000>;
opp-supported-hw = <0x1F 0x0200>;
opp-hz = /bits/ 64 <204000000>;
opp-suspend;
};
opp@312000000,850 {

16
arch/arm/boot/dts/tegra30-ouya.dts
View File

@ -139,6 +139,7 @@ pmic: pmic@2d {
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
wakeup-source;
ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>;
ti,system-power-controller;
@ -391,19 +392,23 @@ cpu0: cpu@0 {
cpu-supply = <&vdd_cpu>;
#cooling-cells = <2>;
};
cpu@1 {
cpu1: cpu@1 {
operating-points-v2 = <&cpu0_opp_table>;
cpu-supply = <&vdd_cpu>;
#cooling-cells = <2>;
};
cpu@2 {
cpu2: cpu@2 {
operating-points-v2 = <&cpu0_opp_table>;
cpu-supply = <&vdd_cpu>;
#cooling-cells = <2>;
};
cpu@3 {
cpu3: cpu@3 {
operating-points-v2 = <&cpu0_opp_table>;
cpu-supply = <&vdd_cpu>;
#cooling-cells = <2>;
};
};
@ -455,7 +460,10 @@ map0 {
};
map1 {
trip = <&cpu_alert1>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

3
arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
View File

@ -128,12 +128,14 @@ opp@204000000,1000 {
opp-microvolt = <1000000 1000000 1350000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0007>;
opp-suspend;
};
opp@204000000,1250 {
opp-microvolt = <1250000 1250000 1350000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0008>;
opp-suspend;
};
opp@333500000,1000 {
@ -312,6 +314,7 @@ opp@204000000 {
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x000F>;
opp-peak-kBps = <1632000>;
opp-suspend;
};
opp@333500000 {