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drm/i915/xe3: Restrict PTL intel_encoder_is_c10phy() to only PHY A

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On PTL, no combo PHY is connected to PORT B. However, PORT B can
still be used for Type-C and will utilize the C20 PHY for eDP
over Type-C. In such configurations, VBTs also enumerate PORT B.

This leads to issues where PORT B is incorrectly identified as using the
C10 PHY, due to the assumption that returning true for PORT B in
intel_encoder_is_c10phy() would not cause problems.

From PTL's perspective, only PORT A/PHY A uses the C10 PHY.

Update the helper intel_encoder_is_c10phy() to return true only for
PORT A/PHY on PTL.

v2: Change the condition code style for ptl/wcl

Bspec: 72571,73944
Fixes: 9d10de78a3 ("drm/i915/wcl: C10 phy connected to port A and B")
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20250922150317.2334680-4-dnyaneshwar.bhadane@intel.com
This commit is contained in:
Dnyaneshwar Bhadane 2025-09-22 20:33:17 +05:30 committed by Suraj Kandpal
parent 4dfaae643e
commit 8147f7a1c0
1 changed files with 6 additions and 8 deletions
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14
drivers/gpu/drm/i915/display/intel_cx0_phy.c
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@ -39,14 +39,12 @@ bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
/* PTL doesn't have a PHY connected to PORT B; as such,
* there will never be a case where PTL uses PHY B.
* WCL uses PORT A and B with the C10 PHY.
* Reusing the condition for WCL and extending it for PORT B
* should not cause any issues for PTL.
*/
if (display->platform.pantherlake && phy < PHY_C)
return true;
if (display->platform.pantherlake) {
if (display->platform.pantherlake_wildcatlake)
return phy <= PHY_B;
else
return phy == PHY_A;
}
if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C)
return true;