github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-30 18:13:41 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

ARM: dts: imx: move nand related property under nand@0

Browse Source 
Add child node nand@0 and move NAND related property under it to align
modern nand-controller.yaml.

Fix below CHECK_DTBS warnings:
  arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtb: nand-controller@1806000 (fsl,imx6q-gpmi-nand): Unevaluated properties are not allowed ('nand-ecc-mode', 'nand-ecc-step-size', 'nand-ecc-strength', 'nand-on-flash-bbt' were unexpected)
        from schema $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#

Since 2019 year, commit
(212e496935 dt-bindings: mtd: Add YAML schemas for the generic NAND options)
NAND related property is preferred located under nand@<n> even though only
one NAND chip supported.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Frank Li 2025-11-04 17:27:14 -05:00 committed by Shawn Guo
parent af6c4ea19d
commit 8124b4a4a9
15 changed files with 82 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi
View File

@ -36,8 +36,12 @@ &clks {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c3 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi
View File

@ -172,8 +172,12 @@ eth_phy: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi
View File

@ -102,8 +102,12 @@ ethphy: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
View File

@ -73,8 +73,12 @@ ethphy: ethernet-phy@3 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c3 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi
View File

@ -260,10 +260,14 @@ fixed-link {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c3 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi
View File

@ -252,9 +252,13 @@ etnphy: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
View File

@ -133,8 +133,12 @@ ethphy1: ethernet-phy@1 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi
View File

@ -101,8 +101,12 @@ ethphy0: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi
View File

@ -63,8 +63,12 @@ ethphy1: ethernet-phy@1 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi
View File

@ -296,9 +296,13 @@ &fec2 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c2 {

12
arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi
View File

@ -160,11 +160,15 @@ &gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
fsl,use-minimum-ecc;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
};
};
/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */

12
arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi
View File

@ -43,11 +43,15 @@ ethphy0: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-ecc-mode = "hw";
nand-ecc-strength = <0>;
nand-ecc-step-size = <0>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-mode = "hw";
nand-ecc-strength = <0>;
nand-ecc-step-size = <0>;
nand-on-flash-bbt;
};
};
&iomuxc {

6
arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi
View File

@ -60,8 +60,12 @@ ethphy0: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&uart1 {

6
arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts
View File

@ -25,8 +25,12 @@ usdhc2_pwrseq: usdhc2-pwrseq {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&snvs_poweroff {

8
arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi
View File

@ -375,10 +375,14 @@ &gpio7 {
/* NAND on such SKUs */
&gpmi {
fsl,use-minimum-ecc;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand@0 {
reg = <0>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
};
};
/* On-module Power I2C */