mirror of
https://github.com/torvalds/linux.git
synced 2026-05-23 22:52:19 +02:00
clk: renesas: Updates for v5.18
- Add DMA engine (SYS-DMAC) clocks on R-Car S4-8, - Add MOST (MediaLB I/F) clocks on R-Car E3 and D3, - Add CAN-FD clocks on R-Car V3U, - Add support for the new RZ/V2L SoC, - Miscellaneous fixes and improvements. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYgZnpQAKCRCKwlD9ZEnx cBXAAQDpW9Ivg1vXbO8PIabhJi7vf/eUOpsP79axIx3vTTZcTwD+LJksYo9HgS0y JwlNLwR6JvAxA1vgrXMFR4yLHdaOnQY= =3jsU -----END PGP SIGNATURE----- Merge tag 'renesas-clk-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8 - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3 - Add CAN-FD clocks on Renesas R-Car V3U - Add support for the new Renesas RZ/V2L SoC - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC dt-bindings: clock: renesas: Document RZ/V2L SoC dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions clk: renesas: r8a779a0: Add CANFD module clock clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3 clk: renesas: r8a7799[05]: Add MLP clocks clk: renesas: r8a779f0: Add SYS-DMAC clocks
This commit is contained in:
Stephen Boyd
commit
80a6359f1c
|
|
@ -4,13 +4,13 @@
|
|||
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode
|
||||
title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description: |
|
||||
On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module
|
||||
On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
|
||||
Standby Mode share the same register block.
|
||||
|
||||
They provide the following functionalities:
|
||||
|
|
@ -22,7 +22,9 @@ description: |
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
|
||||
enum:
|
||||
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-cpg # RZ/V2L
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -40,9 +42,9 @@ properties:
|
|||
description: |
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
and a core clock reference, as defined in
|
||||
<dt-bindings/clock/r9a07g044-cpg.h>
|
||||
<dt-bindings/clock/r9a07g*-cpg.h>
|
||||
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
|
||||
a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.
|
||||
a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
|
||||
const: 2
|
||||
|
||||
'#power-domain-cells':
|
||||
|
|
@ -56,7 +58,7 @@ properties:
|
|||
'#reset-cells':
|
||||
description:
|
||||
The single reset specifier cell must be the module number, as defined in
|
||||
the <dt-bindings/clock/r9a07g044-cpg.h>.
|
||||
the <dt-bindings/clock/r9a07g0*-cpg.h>.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ config CLK_RENESAS
|
|||
select CLK_R8A779F0 if ARCH_R8A779F0
|
||||
select CLK_R9A06G032 if ARCH_R9A06G032
|
||||
select CLK_R9A07G044 if ARCH_R9A07G044
|
||||
select CLK_R9A07G054 if ARCH_R9A07G054
|
||||
select CLK_SH73A0 if ARCH_SH73A0
|
||||
|
||||
if CLK_RENESAS
|
||||
|
|
@ -163,6 +164,10 @@ config CLK_R9A07G044
|
|||
bool "RZ/G2L clock support" if COMPILE_TEST
|
||||
select CLK_RZG2L
|
||||
|
||||
config CLK_R9A07G054
|
||||
bool "RZ/V2L clock support" if COMPILE_TEST
|
||||
select CLK_RZG2L
|
||||
|
||||
config CLK_SH73A0
|
||||
bool "SH-Mobile AG5 clock support" if COMPILE_TEST
|
||||
select CLK_RENESAS_CPG_MSTP
|
||||
|
|
@ -195,7 +200,7 @@ config CLK_RCAR_USB2_CLOCK_SEL
|
|||
This is a driver for R-Car USB2 clock selector
|
||||
|
||||
config CLK_RZG2L
|
||||
bool "Renesas RZ/G2L family clock support" if COMPILE_TEST
|
||||
bool "Renesas RZ/{G2L,V2L} family clock support" if COMPILE_TEST
|
||||
select RESET_CONTROLLER
|
||||
|
||||
# Generic
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
|
|||
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
|
||||
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
|
||||
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
|
||||
|
||||
# Family
|
||||
|
|
|
|||
|
|
@ -200,6 +200,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
|
|||
DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
|
||||
DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),
|
||||
|
||||
DEF_MOD("mlp", 802, R8A77990_CLK_S2D1),
|
||||
DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("vin4", 807, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2),
|
||||
|
|
|
|||
|
|
@ -160,6 +160,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
|
|||
DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("mlp", 802, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
|
||||
|
|
|
|||
|
|
@ -136,6 +136,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
|
|||
DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2),
|
||||
DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2),
|
||||
DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2),
|
||||
DEF_MOD("canfd0", 328, R8A779A0_CLK_CANFD),
|
||||
DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
|
||||
DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
|
||||
DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
|
||||
|
|
|
|||
|
|
@ -119,6 +119,8 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
|
|||
DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER),
|
||||
DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER),
|
||||
DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER),
|
||||
DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER),
|
||||
DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER),
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -11,12 +11,13 @@
|
|||
#include <linux/kernel.h>
|
||||
|
||||
#include <dt-bindings/clock/r9a07g044-cpg.h>
|
||||
#include <dt-bindings/clock/r9a07g054-cpg.h>
|
||||
|
||||
#include "rzg2l-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2,
|
||||
LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
|
|
@ -80,200 +81,222 @@ static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
|
|||
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
|
||||
static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
|
||||
|
||||
static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
static const struct {
|
||||
struct cpg_core_clk common[44];
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
struct cpg_core_clk drp[0];
|
||||
#endif
|
||||
} core_clks __initconst = {
|
||||
.common = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
|
||||
DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
|
||||
DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
|
||||
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
|
||||
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),
|
||||
DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
|
||||
DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
|
||||
/* Internal Core Clocks */
|
||||
DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
|
||||
DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
|
||||
DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
|
||||
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
|
||||
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
|
||||
DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
|
||||
DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
|
||||
|
||||
DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
|
||||
DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6),
|
||||
DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
|
||||
DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6),
|
||||
|
||||
DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
|
||||
DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
|
||||
|
||||
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
|
||||
DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
|
||||
DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
|
||||
DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
|
||||
DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
|
||||
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
|
||||
DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
|
||||
DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
|
||||
DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
|
||||
DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
|
||||
|
||||
DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
|
||||
DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
|
||||
DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
|
||||
DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
|
||||
|
||||
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
|
||||
DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
|
||||
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
|
||||
DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
|
||||
DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
|
||||
sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
|
||||
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
|
||||
DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
|
||||
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
|
||||
DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
|
||||
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
|
||||
DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
|
||||
DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
|
||||
sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
|
||||
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
|
||||
DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
|
||||
|
||||
DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
|
||||
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
|
||||
DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2,
|
||||
sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY),
|
||||
DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
|
||||
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
|
||||
DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2,
|
||||
sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY),
|
||||
|
||||
/* Core output clk */
|
||||
DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
|
||||
CLK_DIVIDER_HIWORD_MASK),
|
||||
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
|
||||
dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
|
||||
DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
|
||||
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
|
||||
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
|
||||
DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
|
||||
DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
|
||||
DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
|
||||
DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
|
||||
DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
|
||||
DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
|
||||
DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2,
|
||||
sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
|
||||
DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
|
||||
DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
|
||||
DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0,
|
||||
sel_shdi, ARRAY_SIZE(sel_shdi)),
|
||||
DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1,
|
||||
sel_shdi, ARRAY_SIZE(sel_shdi)),
|
||||
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
|
||||
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
|
||||
DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
|
||||
CLK_DIVIDER_HIWORD_MASK),
|
||||
/* Core output clk */
|
||||
DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
|
||||
CLK_DIVIDER_HIWORD_MASK),
|
||||
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
|
||||
dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
|
||||
DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
|
||||
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
|
||||
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
|
||||
DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
|
||||
DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
|
||||
DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
|
||||
DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
|
||||
DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
|
||||
DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
|
||||
DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2,
|
||||
sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
|
||||
DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
|
||||
DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
|
||||
DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0,
|
||||
sel_shdi, ARRAY_SIZE(sel_shdi)),
|
||||
DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1,
|
||||
sel_shdi, ARRAY_SIZE(sel_shdi)),
|
||||
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
|
||||
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
|
||||
DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
|
||||
CLK_DIVIDER_HIWORD_MASK),
|
||||
},
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
.drp = {
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
|
||||
DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
|
||||
0x514, 0),
|
||||
DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
|
||||
0x518, 0),
|
||||
DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
|
||||
0x518, 1),
|
||||
DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
|
||||
0x52c, 0),
|
||||
DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
|
||||
0x52c, 1),
|
||||
DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
|
||||
0x534, 0),
|
||||
DEF_MOD("ostm1_clk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
|
||||
0x534, 1),
|
||||
DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
|
||||
0x534, 2),
|
||||
DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
|
||||
0x548, 0),
|
||||
DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
|
||||
0x548, 1),
|
||||
DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0,
|
||||
0x548, 2),
|
||||
DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
|
||||
0x548, 3),
|
||||
DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0,
|
||||
0x548, 4),
|
||||
DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK,
|
||||
0x548, 5),
|
||||
DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
|
||||
0x550, 0),
|
||||
DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
|
||||
0x550, 1),
|
||||
DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,
|
||||
0x554, 0),
|
||||
DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,
|
||||
0x554, 1),
|
||||
DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,
|
||||
0x554, 2),
|
||||
DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,
|
||||
0x554, 3),
|
||||
DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,
|
||||
0x554, 4),
|
||||
DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,
|
||||
0x554, 5),
|
||||
DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,
|
||||
0x554, 6),
|
||||
DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
|
||||
0x554, 7),
|
||||
DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
|
||||
0x558, 0),
|
||||
DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
|
||||
0x558, 1),
|
||||
DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
|
||||
0x558, 2),
|
||||
DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
|
||||
0x570, 0),
|
||||
DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
|
||||
0x570, 1),
|
||||
DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
|
||||
0x570, 2),
|
||||
DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
|
||||
0x570, 3),
|
||||
DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
|
||||
0x570, 4),
|
||||
DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
|
||||
0x570, 5),
|
||||
DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
|
||||
0x570, 6),
|
||||
DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
|
||||
0x570, 7),
|
||||
DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
|
||||
0x578, 0),
|
||||
DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
|
||||
0x578, 1),
|
||||
DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
|
||||
0x578, 2),
|
||||
DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
|
||||
0x578, 3),
|
||||
DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0,
|
||||
0x57c, 0),
|
||||
DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT,
|
||||
0x57c, 0),
|
||||
DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0,
|
||||
0x57c, 1),
|
||||
DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT,
|
||||
0x57c, 1),
|
||||
DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
|
||||
0x580, 0),
|
||||
DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
|
||||
0x580, 1),
|
||||
DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
|
||||
0x580, 2),
|
||||
DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
|
||||
0x580, 3),
|
||||
DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
|
||||
0x584, 0),
|
||||
DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
|
||||
0x584, 1),
|
||||
DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
|
||||
0x584, 2),
|
||||
DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
|
||||
0x584, 3),
|
||||
DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
|
||||
0x584, 4),
|
||||
DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
|
||||
0x588, 0),
|
||||
DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,
|
||||
0x588, 1),
|
||||
DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0,
|
||||
0x590, 0),
|
||||
DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0,
|
||||
0x590, 1),
|
||||
DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0,
|
||||
0x590, 2),
|
||||
DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
|
||||
0x594, 0),
|
||||
DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
|
||||
0x598, 0),
|
||||
DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
|
||||
0x5a8, 0),
|
||||
DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
|
||||
0x5a8, 1),
|
||||
DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,
|
||||
0x5ac, 0),
|
||||
static const struct {
|
||||
struct rzg2l_mod_clk common[62];
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
struct rzg2l_mod_clk drp[0];
|
||||
#endif
|
||||
} mod_clks = {
|
||||
.common = {
|
||||
DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
|
||||
0x514, 0),
|
||||
DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
|
||||
0x518, 0),
|
||||
DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
|
||||
0x518, 1),
|
||||
DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
|
||||
0x52c, 0),
|
||||
DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
|
||||
0x52c, 1),
|
||||
DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
|
||||
0x534, 0),
|
||||
DEF_MOD("ostm1_clk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
|
||||
0x534, 1),
|
||||
DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
|
||||
0x534, 2),
|
||||
DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
|
||||
0x548, 0),
|
||||
DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
|
||||
0x548, 1),
|
||||
DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0,
|
||||
0x548, 2),
|
||||
DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
|
||||
0x548, 3),
|
||||
DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0,
|
||||
0x548, 4),
|
||||
DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK,
|
||||
0x548, 5),
|
||||
DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
|
||||
0x550, 0),
|
||||
DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
|
||||
0x550, 1),
|
||||
DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,
|
||||
0x554, 0),
|
||||
DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,
|
||||
0x554, 1),
|
||||
DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,
|
||||
0x554, 2),
|
||||
DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,
|
||||
0x554, 3),
|
||||
DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,
|
||||
0x554, 4),
|
||||
DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,
|
||||
0x554, 5),
|
||||
DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,
|
||||
0x554, 6),
|
||||
DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
|
||||
0x554, 7),
|
||||
DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
|
||||
0x558, 0),
|
||||
DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
|
||||
0x558, 1),
|
||||
DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
|
||||
0x558, 2),
|
||||
DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
|
||||
0x570, 0),
|
||||
DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
|
||||
0x570, 1),
|
||||
DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
|
||||
0x570, 2),
|
||||
DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
|
||||
0x570, 3),
|
||||
DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
|
||||
0x570, 4),
|
||||
DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
|
||||
0x570, 5),
|
||||
DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
|
||||
0x570, 6),
|
||||
DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
|
||||
0x570, 7),
|
||||
DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
|
||||
0x578, 0),
|
||||
DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
|
||||
0x578, 1),
|
||||
DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
|
||||
0x578, 2),
|
||||
DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
|
||||
0x578, 3),
|
||||
DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0,
|
||||
0x57c, 0),
|
||||
DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT,
|
||||
0x57c, 0),
|
||||
DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0,
|
||||
0x57c, 1),
|
||||
DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT,
|
||||
0x57c, 1),
|
||||
DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
|
||||
0x580, 0),
|
||||
DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
|
||||
0x580, 1),
|
||||
DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
|
||||
0x580, 2),
|
||||
DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
|
||||
0x580, 3),
|
||||
DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
|
||||
0x584, 0),
|
||||
DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
|
||||
0x584, 1),
|
||||
DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
|
||||
0x584, 2),
|
||||
DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
|
||||
0x584, 3),
|
||||
DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
|
||||
0x584, 4),
|
||||
DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
|
||||
0x588, 0),
|
||||
DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,
|
||||
0x588, 1),
|
||||
DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0,
|
||||
0x590, 0),
|
||||
DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0,
|
||||
0x590, 1),
|
||||
DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0,
|
||||
0x590, 2),
|
||||
DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
|
||||
0x594, 0),
|
||||
DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
|
||||
0x598, 0),
|
||||
DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
|
||||
0x5a8, 0),
|
||||
DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
|
||||
0x5a8, 1),
|
||||
DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,
|
||||
0x5ac, 0),
|
||||
},
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
.drp = {
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct rzg2l_reset r9a07g044_resets[] = {
|
||||
|
|
@ -336,8 +359,8 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
|
|||
|
||||
const struct rzg2l_cpg_info r9a07g044_cpg_info = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r9a07g044_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
|
||||
.core_clks = core_clks.common,
|
||||
.num_core_clks = ARRAY_SIZE(core_clks.common),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
|
|
@ -346,11 +369,34 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
|
|||
.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r9a07g044_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
|
||||
.mod_clks = mod_clks.common,
|
||||
.num_mod_clks = ARRAY_SIZE(mod_clks.common),
|
||||
.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
|
||||
|
||||
/* Resets */
|
||||
.resets = r9a07g044_resets,
|
||||
.num_resets = ARRAY_SIZE(r9a07g044_resets),
|
||||
.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
const struct rzg2l_cpg_info r9a07g054_cpg_info = {
|
||||
/* Core Clocks */
|
||||
.core_clks = core_clks.common,
|
||||
.num_core_clks = ARRAY_SIZE(core_clks.common) + ARRAY_SIZE(core_clks.drp),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r9a07g044_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = mod_clks.common,
|
||||
.num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp),
|
||||
.num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,
|
||||
|
||||
/* Resets */
|
||||
.resets = r9a07g044_resets,
|
||||
.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -952,6 +952,12 @@ static const struct of_device_id rzg2l_cpg_match[] = {
|
|||
.compatible = "renesas,r9a07g044-cpg",
|
||||
.data = &r9a07g044_cpg_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
{
|
||||
.compatible = "renesas,r9a07g054-cpg",
|
||||
.data = &r9a07g054_cpg_info,
|
||||
},
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -203,5 +203,6 @@ struct rzg2l_cpg_info {
|
|||
};
|
||||
|
||||
extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
|
||||
extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
229
include/dt-bindings/clock/r9a07g054-cpg.h
Normal file
229
include/dt-bindings/clock/r9a07g054-cpg.h
Normal file
|
|
@ -0,0 +1,229 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
*
|
||||
* Copyright (C) 2022 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__
|
||||
#define __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* R9A07G054 CPG Core Clocks */
|
||||
#define R9A07G054_CLK_I 0
|
||||
#define R9A07G054_CLK_I2 1
|
||||
#define R9A07G054_CLK_G 2
|
||||
#define R9A07G054_CLK_S0 3
|
||||
#define R9A07G054_CLK_S1 4
|
||||
#define R9A07G054_CLK_SPI0 5
|
||||
#define R9A07G054_CLK_SPI1 6
|
||||
#define R9A07G054_CLK_SD0 7
|
||||
#define R9A07G054_CLK_SD1 8
|
||||
#define R9A07G054_CLK_M0 9
|
||||
#define R9A07G054_CLK_M1 10
|
||||
#define R9A07G054_CLK_M2 11
|
||||
#define R9A07G054_CLK_M3 12
|
||||
#define R9A07G054_CLK_M4 13
|
||||
#define R9A07G054_CLK_HP 14
|
||||
#define R9A07G054_CLK_TSU 15
|
||||
#define R9A07G054_CLK_ZT 16
|
||||
#define R9A07G054_CLK_P0 17
|
||||
#define R9A07G054_CLK_P1 18
|
||||
#define R9A07G054_CLK_P2 19
|
||||
#define R9A07G054_CLK_AT 20
|
||||
#define R9A07G054_OSCCLK 21
|
||||
#define R9A07G054_CLK_P0_DIV2 22
|
||||
#define R9A07G054_CLK_DRP_M 23
|
||||
#define R9A07G054_CLK_DRP_D 24
|
||||
#define R9A07G054_CLK_DRP_A 25
|
||||
|
||||
/* R9A07G054 Module Clocks */
|
||||
#define R9A07G054_CA55_SCLK 0
|
||||
#define R9A07G054_CA55_PCLK 1
|
||||
#define R9A07G054_CA55_ATCLK 2
|
||||
#define R9A07G054_CA55_GICCLK 3
|
||||
#define R9A07G054_CA55_PERICLK 4
|
||||
#define R9A07G054_CA55_ACLK 5
|
||||
#define R9A07G054_CA55_TSCLK 6
|
||||
#define R9A07G054_GIC600_GICCLK 7
|
||||
#define R9A07G054_IA55_CLK 8
|
||||
#define R9A07G054_IA55_PCLK 9
|
||||
#define R9A07G054_MHU_PCLK 10
|
||||
#define R9A07G054_SYC_CNT_CLK 11
|
||||
#define R9A07G054_DMAC_ACLK 12
|
||||
#define R9A07G054_DMAC_PCLK 13
|
||||
#define R9A07G054_OSTM0_PCLK 14
|
||||
#define R9A07G054_OSTM1_PCLK 15
|
||||
#define R9A07G054_OSTM2_PCLK 16
|
||||
#define R9A07G054_MTU_X_MCK_MTU3 17
|
||||
#define R9A07G054_POE3_CLKM_POE 18
|
||||
#define R9A07G054_GPT_PCLK 19
|
||||
#define R9A07G054_POEG_A_CLKP 20
|
||||
#define R9A07G054_POEG_B_CLKP 21
|
||||
#define R9A07G054_POEG_C_CLKP 22
|
||||
#define R9A07G054_POEG_D_CLKP 23
|
||||
#define R9A07G054_WDT0_PCLK 24
|
||||
#define R9A07G054_WDT0_CLK 25
|
||||
#define R9A07G054_WDT1_PCLK 26
|
||||
#define R9A07G054_WDT1_CLK 27
|
||||
#define R9A07G054_WDT2_PCLK 28
|
||||
#define R9A07G054_WDT2_CLK 29
|
||||
#define R9A07G054_SPI_CLK2 30
|
||||
#define R9A07G054_SPI_CLK 31
|
||||
#define R9A07G054_SDHI0_IMCLK 32
|
||||
#define R9A07G054_SDHI0_IMCLK2 33
|
||||
#define R9A07G054_SDHI0_CLK_HS 34
|
||||
#define R9A07G054_SDHI0_ACLK 35
|
||||
#define R9A07G054_SDHI1_IMCLK 36
|
||||
#define R9A07G054_SDHI1_IMCLK2 37
|
||||
#define R9A07G054_SDHI1_CLK_HS 38
|
||||
#define R9A07G054_SDHI1_ACLK 39
|
||||
#define R9A07G054_GPU_CLK 40
|
||||
#define R9A07G054_GPU_AXI_CLK 41
|
||||
#define R9A07G054_GPU_ACE_CLK 42
|
||||
#define R9A07G054_ISU_ACLK 43
|
||||
#define R9A07G054_ISU_PCLK 44
|
||||
#define R9A07G054_H264_CLK_A 45
|
||||
#define R9A07G054_H264_CLK_P 46
|
||||
#define R9A07G054_CRU_SYSCLK 47
|
||||
#define R9A07G054_CRU_VCLK 48
|
||||
#define R9A07G054_CRU_PCLK 49
|
||||
#define R9A07G054_CRU_ACLK 50
|
||||
#define R9A07G054_MIPI_DSI_PLLCLK 51
|
||||
#define R9A07G054_MIPI_DSI_SYSCLK 52
|
||||
#define R9A07G054_MIPI_DSI_ACLK 53
|
||||
#define R9A07G054_MIPI_DSI_PCLK 54
|
||||
#define R9A07G054_MIPI_DSI_VCLK 55
|
||||
#define R9A07G054_MIPI_DSI_LPCLK 56
|
||||
#define R9A07G054_LCDC_CLK_A 57
|
||||
#define R9A07G054_LCDC_CLK_P 58
|
||||
#define R9A07G054_LCDC_CLK_D 59
|
||||
#define R9A07G054_SSI0_PCLK2 60
|
||||
#define R9A07G054_SSI0_PCLK_SFR 61
|
||||
#define R9A07G054_SSI1_PCLK2 62
|
||||
#define R9A07G054_SSI1_PCLK_SFR 63
|
||||
#define R9A07G054_SSI2_PCLK2 64
|
||||
#define R9A07G054_SSI2_PCLK_SFR 65
|
||||
#define R9A07G054_SSI3_PCLK2 66
|
||||
#define R9A07G054_SSI3_PCLK_SFR 67
|
||||
#define R9A07G054_SRC_CLKP 68
|
||||
#define R9A07G054_USB_U2H0_HCLK 69
|
||||
#define R9A07G054_USB_U2H1_HCLK 70
|
||||
#define R9A07G054_USB_U2P_EXR_CPUCLK 71
|
||||
#define R9A07G054_USB_PCLK 72
|
||||
#define R9A07G054_ETH0_CLK_AXI 73
|
||||
#define R9A07G054_ETH0_CLK_CHI 74
|
||||
#define R9A07G054_ETH1_CLK_AXI 75
|
||||
#define R9A07G054_ETH1_CLK_CHI 76
|
||||
#define R9A07G054_I2C0_PCLK 77
|
||||
#define R9A07G054_I2C1_PCLK 78
|
||||
#define R9A07G054_I2C2_PCLK 79
|
||||
#define R9A07G054_I2C3_PCLK 80
|
||||
#define R9A07G054_SCIF0_CLK_PCK 81
|
||||
#define R9A07G054_SCIF1_CLK_PCK 82
|
||||
#define R9A07G054_SCIF2_CLK_PCK 83
|
||||
#define R9A07G054_SCIF3_CLK_PCK 84
|
||||
#define R9A07G054_SCIF4_CLK_PCK 85
|
||||
#define R9A07G054_SCI0_CLKP 86
|
||||
#define R9A07G054_SCI1_CLKP 87
|
||||
#define R9A07G054_IRDA_CLKP 88
|
||||
#define R9A07G054_RSPI0_CLKB 89
|
||||
#define R9A07G054_RSPI1_CLKB 90
|
||||
#define R9A07G054_RSPI2_CLKB 91
|
||||
#define R9A07G054_CANFD_PCLK 92
|
||||
#define R9A07G054_GPIO_HCLK 93
|
||||
#define R9A07G054_ADC_ADCLK 94
|
||||
#define R9A07G054_ADC_PCLK 95
|
||||
#define R9A07G054_TSU_PCLK 96
|
||||
#define R9A07G054_STPAI_INITCLK 97
|
||||
#define R9A07G054_STPAI_ACLK 98
|
||||
#define R9A07G054_STPAI_MCLK 99
|
||||
#define R9A07G054_STPAI_DCLKIN 100
|
||||
#define R9A07G054_STPAI_ACLK_DRP 101
|
||||
|
||||
/* R9A07G054 Resets */
|
||||
#define R9A07G054_CA55_RST_1_0 0
|
||||
#define R9A07G054_CA55_RST_1_1 1
|
||||
#define R9A07G054_CA55_RST_3_0 2
|
||||
#define R9A07G054_CA55_RST_3_1 3
|
||||
#define R9A07G054_CA55_RST_4 4
|
||||
#define R9A07G054_CA55_RST_5 5
|
||||
#define R9A07G054_CA55_RST_6 6
|
||||
#define R9A07G054_CA55_RST_7 7
|
||||
#define R9A07G054_CA55_RST_8 8
|
||||
#define R9A07G054_CA55_RST_9 9
|
||||
#define R9A07G054_CA55_RST_10 10
|
||||
#define R9A07G054_CA55_RST_11 11
|
||||
#define R9A07G054_CA55_RST_12 12
|
||||
#define R9A07G054_GIC600_GICRESET_N 13
|
||||
#define R9A07G054_GIC600_DBG_GICRESET_N 14
|
||||
#define R9A07G054_IA55_RESETN 15
|
||||
#define R9A07G054_MHU_RESETN 16
|
||||
#define R9A07G054_DMAC_ARESETN 17
|
||||
#define R9A07G054_DMAC_RST_ASYNC 18
|
||||
#define R9A07G054_SYC_RESETN 19
|
||||
#define R9A07G054_OSTM0_PRESETZ 20
|
||||
#define R9A07G054_OSTM1_PRESETZ 21
|
||||
#define R9A07G054_OSTM2_PRESETZ 22
|
||||
#define R9A07G054_MTU_X_PRESET_MTU3 23
|
||||
#define R9A07G054_POE3_RST_M_REG 24
|
||||
#define R9A07G054_GPT_RST_C 25
|
||||
#define R9A07G054_POEG_A_RST 26
|
||||
#define R9A07G054_POEG_B_RST 27
|
||||
#define R9A07G054_POEG_C_RST 28
|
||||
#define R9A07G054_POEG_D_RST 29
|
||||
#define R9A07G054_WDT0_PRESETN 30
|
||||
#define R9A07G054_WDT1_PRESETN 31
|
||||
#define R9A07G054_WDT2_PRESETN 32
|
||||
#define R9A07G054_SPI_RST 33
|
||||
#define R9A07G054_SDHI0_IXRST 34
|
||||
#define R9A07G054_SDHI1_IXRST 35
|
||||
#define R9A07G054_GPU_RESETN 36
|
||||
#define R9A07G054_GPU_AXI_RESETN 37
|
||||
#define R9A07G054_GPU_ACE_RESETN 38
|
||||
#define R9A07G054_ISU_ARESETN 39
|
||||
#define R9A07G054_ISU_PRESETN 40
|
||||
#define R9A07G054_H264_X_RESET_VCP 41
|
||||
#define R9A07G054_H264_CP_PRESET_P 42
|
||||
#define R9A07G054_CRU_CMN_RSTB 43
|
||||
#define R9A07G054_CRU_PRESETN 44
|
||||
#define R9A07G054_CRU_ARESETN 45
|
||||
#define R9A07G054_MIPI_DSI_CMN_RSTB 46
|
||||
#define R9A07G054_MIPI_DSI_ARESET_N 47
|
||||
#define R9A07G054_MIPI_DSI_PRESET_N 48
|
||||
#define R9A07G054_LCDC_RESET_N 49
|
||||
#define R9A07G054_SSI0_RST_M2_REG 50
|
||||
#define R9A07G054_SSI1_RST_M2_REG 51
|
||||
#define R9A07G054_SSI2_RST_M2_REG 52
|
||||
#define R9A07G054_SSI3_RST_M2_REG 53
|
||||
#define R9A07G054_SRC_RST 54
|
||||
#define R9A07G054_USB_U2H0_HRESETN 55
|
||||
#define R9A07G054_USB_U2H1_HRESETN 56
|
||||
#define R9A07G054_USB_U2P_EXL_SYSRST 57
|
||||
#define R9A07G054_USB_PRESETN 58
|
||||
#define R9A07G054_ETH0_RST_HW_N 59
|
||||
#define R9A07G054_ETH1_RST_HW_N 60
|
||||
#define R9A07G054_I2C0_MRST 61
|
||||
#define R9A07G054_I2C1_MRST 62
|
||||
#define R9A07G054_I2C2_MRST 63
|
||||
#define R9A07G054_I2C3_MRST 64
|
||||
#define R9A07G054_SCIF0_RST_SYSTEM_N 65
|
||||
#define R9A07G054_SCIF1_RST_SYSTEM_N 66
|
||||
#define R9A07G054_SCIF2_RST_SYSTEM_N 67
|
||||
#define R9A07G054_SCIF3_RST_SYSTEM_N 68
|
||||
#define R9A07G054_SCIF4_RST_SYSTEM_N 69
|
||||
#define R9A07G054_SCI0_RST 70
|
||||
#define R9A07G054_SCI1_RST 71
|
||||
#define R9A07G054_IRDA_RST 72
|
||||
#define R9A07G054_RSPI0_RST 73
|
||||
#define R9A07G054_RSPI1_RST 74
|
||||
#define R9A07G054_RSPI2_RST 75
|
||||
#define R9A07G054_CANFD_RSTP_N 76
|
||||
#define R9A07G054_CANFD_RSTC_N 77
|
||||
#define R9A07G054_GPIO_RSTN 78
|
||||
#define R9A07G054_GPIO_PORT_RESETN 79
|
||||
#define R9A07G054_GPIO_SPARE_RESETN 80
|
||||
#define R9A07G054_ADC_PRESETN 81
|
||||
#define R9A07G054_ADC_ADRST_N 82
|
||||
#define R9A07G054_TSU_PRESETN 83
|
||||
#define R9A07G054_STPAI_ARESETN 84
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
|
||||
Loading…
Reference in New Issue
Block a user