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crypto: hisilicon - enable error reporting again

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When an error occurs on the device, an interrupt is reported.
When the firmware forwards the interrupt to the driver and masks the
error. If the driver does not enable error reporting when an error does
not need to be reset, the device does not report the error to the driver
when the error occurs again. Therefore, after the driver obtains the
information, the error reporting needs to be enabled again.

Signed-off-by: Weili Qian <qianweili@huawei.com>
Signed-off-by: Chenghai Huang <huangchenghai2@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Weili Qian 2025-09-13 18:57:52 +08:00 committed by Herbert Xu
parent 3d716c51e0
commit 80736a97cf
4 changed files with 41 additions and 0 deletions
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11
drivers/crypto/hisilicon/hpre/hpre_main.c
View File

@ -1399,6 +1399,15 @@ static void hpre_disable_error_report(struct hisi_qm *qm, u32 err_type)
writel(nfe_mask & (~err_type), qm->io_base + HPRE_RAS_NFE_ENB);
}
static void hpre_enable_error_report(struct hisi_qm *qm)
{
u32 nfe_mask = qm->err_info.dev_err.nfe;
u32 ce_mask = qm->err_info.dev_err.ce;
writel(nfe_mask, qm->io_base + HPRE_RAS_NFE_ENB);
writel(ce_mask, qm->io_base + HPRE_RAS_CE_ENB);
}
static void hpre_open_axi_master_ooo(struct hisi_qm *qm)
{
u32 value;
@ -1426,6 +1435,8 @@ static enum acc_err_result hpre_get_err_result(struct hisi_qm *qm)
return ACC_ERR_NEED_RESET;
}
hpre_clear_hw_err_status(qm, err_status);
/* Avoid firmware disable error report, re-enable. */
hpre_enable_error_report(qm);
}
return ACC_ERR_RECOVERED;

11
drivers/crypto/hisilicon/sec2/sec_main.c
View File

@ -1112,6 +1112,15 @@ static void sec_disable_error_report(struct hisi_qm *qm, u32 err_type)
writel(nfe_mask & (~err_type), qm->io_base + SEC_RAS_NFE_REG);
}
static void sec_enable_error_report(struct hisi_qm *qm)
{
u32 nfe_mask = qm->err_info.dev_err.nfe;
u32 ce_mask = qm->err_info.dev_err.ce;
writel(nfe_mask, qm->io_base + SEC_RAS_NFE_REG);
writel(ce_mask, qm->io_base + SEC_RAS_CE_REG);
}
static void sec_open_axi_master_ooo(struct hisi_qm *qm)
{
u32 val;
@ -1137,6 +1146,8 @@ static enum acc_err_result sec_get_err_result(struct hisi_qm *qm)
return ACC_ERR_NEED_RESET;
}
sec_clear_hw_err_status(qm, err_status);
/* Avoid firmware disable error report, re-enable. */
sec_enable_error_report(qm);
}
return ACC_ERR_RECOVERED;

8
drivers/crypto/hisilicon/zip/dae_main.c
View File

@ -175,6 +175,12 @@ static void hisi_dae_disable_error_report(struct hisi_qm *qm, u32 err_type)
writel(DAE_ERR_NFE_MASK & (~err_type), qm->io_base + DAE_ERR_NFE_OFFSET);
}
static void hisi_dae_enable_error_report(struct hisi_qm *qm)
{
writel(DAE_ERR_CE_MASK, qm->io_base + DAE_ERR_CE_OFFSET);
writel(DAE_ERR_NFE_MASK, qm->io_base + DAE_ERR_NFE_OFFSET);
}
static void hisi_dae_log_hw_error(struct hisi_qm *qm, u32 err_type)
{
const struct hisi_dae_hw_error *err = dae_hw_error;
@ -216,6 +222,8 @@ enum acc_err_result hisi_dae_get_err_result(struct hisi_qm *qm)
return ACC_ERR_NEED_RESET;
}
hisi_dae_clear_hw_err_status(qm, err_status);
/* Avoid firmware disable error report, re-enable. */
hisi_dae_enable_error_report(qm);
return ACC_ERR_RECOVERED;
}

11
drivers/crypto/hisilicon/zip/zip_main.c
View File

@ -1188,6 +1188,15 @@ static void hisi_zip_disable_error_report(struct hisi_qm *qm, u32 err_type)
writel(nfe_mask & (~err_type), qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
}
static void hisi_zip_enable_error_report(struct hisi_qm *qm)
{
u32 nfe_mask = qm->err_info.dev_err.nfe;
u32 ce_mask = qm->err_info.dev_err.ce;
writel(nfe_mask, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
writel(ce_mask, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);
}
static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm)
{
u32 val;
@ -1236,6 +1245,8 @@ static enum acc_err_result hisi_zip_get_err_result(struct hisi_qm *qm)
zip_result = ACC_ERR_NEED_RESET;
} else {
hisi_zip_clear_hw_err_status(qm, err_status);
/* Avoid firmware disable error report, re-enable. */
hisi_zip_enable_error_report(qm);
}
}