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drm/panel: xinpeng-xpp055c272: transition to mipi_dsi wrapped functions
Changes the xinpeng-xpp055c272 panel to use multi style functions for improved error handling. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Tejas Vipin <tejasvipin76@gmail.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20250107092510.174089-1-tejasvipin76@gmail.com
This commit is contained in:
Tejas Vipin
Douglas Anderson
parent
0d6c9edf9e
commit
8025f23728
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@ -59,91 +59,80 @@ static inline struct xpp055c272 *panel_to_xpp055c272(struct drm_panel *panel)
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return container_of(panel, struct xpp055c272, panel);
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}
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static int xpp055c272_init_sequence(struct xpp055c272 *ctx)
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static void xpp055c272_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
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{
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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struct device *dev = ctx->dev;
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/*
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* Init sequence was supplied by the panel vendor without much
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* documentation.
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*/
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETEXTC, 0xf1, 0x12, 0x83);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETMIPI,
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0x33, 0x81, 0x05, 0xf9, 0x0e, 0x0e, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x25,
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0x00, 0x91, 0x0a, 0x00, 0x00, 0x02, 0x4f, 0x01,
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0x00, 0x00, 0x37);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPOWER_EXT, 0x25);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPCR, 0x02, 0x11, 0x00);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETRGBIF,
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0x0c, 0x10, 0x0a, 0x50, 0x03, 0xff, 0x00, 0x00,
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0x00, 0x00);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETSCR,
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0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70,
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0x00);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETVDC, 0x46);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPANEL, 0x0b);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETCYC, 0x80);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETDISP, 0xc8, 0x12, 0x30);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETEQ,
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0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00,
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0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPOWER,
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0x53, 0x00, 0x1e, 0x1e, 0x77, 0xe1, 0xcc, 0xdd,
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0x67, 0x77, 0x33, 0x33);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETECO, 0x00, 0x00, 0xff,
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0xff, 0x01, 0xff);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETBGP, 0x09, 0x09);
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msleep(20);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETEXTC, 0xf1, 0x12, 0x83);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETMIPI,
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0x33, 0x81, 0x05, 0xf9, 0x0e, 0x0e, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x25,
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0x00, 0x91, 0x0a, 0x00, 0x00, 0x02, 0x4f, 0x01,
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0x00, 0x00, 0x37);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETPOWER_EXT, 0x25);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETPCR, 0x02, 0x11, 0x00);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETRGBIF,
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0x0c, 0x10, 0x0a, 0x50, 0x03, 0xff, 0x00, 0x00,
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0x00, 0x00);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETSCR,
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0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70,
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0x00);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETVDC, 0x46);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETPANEL, 0x0b);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETCYC, 0x80);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETDISP, 0xc8, 0x12, 0x30);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETEQ,
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0x07, 0x07, 0x0b, 0x0b, 0x03, 0x0b, 0x00, 0x00,
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0x00, 0x00, 0xff, 0x00, 0xC0, 0x10);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETPOWER,
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0x53, 0x00, 0x1e, 0x1e, 0x77, 0xe1, 0xcc, 0xdd,
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0x67, 0x77, 0x33, 0x33);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETECO, 0x00, 0x00, 0xff,
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0xff, 0x01, 0xff);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETBGP, 0x09, 0x09);
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mipi_dsi_msleep(dsi_ctx, 20);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETVCOM, 0x87, 0x95);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGIP1,
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0xc2, 0x10, 0x05, 0x05, 0x10, 0x05, 0xa0, 0x12,
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0x31, 0x23, 0x3f, 0x81, 0x0a, 0xa0, 0x37, 0x18,
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0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80,
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0x01, 0x00, 0x00, 0x00, 0x48, 0xf8, 0x86, 0x42,
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0x08, 0x88, 0x88, 0x80, 0x88, 0x88, 0x88, 0x58,
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0xf8, 0x87, 0x53, 0x18, 0x88, 0x88, 0x81, 0x88,
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0x88, 0x88, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGIP2,
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0x00, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x1f, 0x88, 0x81, 0x35,
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0x78, 0x88, 0x88, 0x85, 0x88, 0x88, 0x88, 0x0f,
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0x88, 0x80, 0x24, 0x68, 0x88, 0x88, 0x84, 0x88,
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0x88, 0x88, 0x23, 0x10, 0x00, 0x00, 0x1c, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x05,
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0xa0, 0x00, 0x00, 0x00, 0x00);
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mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGAMMA,
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0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38, 0x36,
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0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13, 0x11,
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0x18, 0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38,
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0x36, 0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13,
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0x11, 0x18);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETVCOM, 0x87, 0x95);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETGIP1,
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0xc2, 0x10, 0x05, 0x05, 0x10, 0x05, 0xa0, 0x12,
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0x31, 0x23, 0x3f, 0x81, 0x0a, 0xa0, 0x37, 0x18,
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0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80,
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0x01, 0x00, 0x00, 0x00, 0x48, 0xf8, 0x86, 0x42,
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0x08, 0x88, 0x88, 0x80, 0x88, 0x88, 0x88, 0x58,
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0xf8, 0x87, 0x53, 0x18, 0x88, 0x88, 0x81, 0x88,
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0x88, 0x88, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETGIP2,
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0x00, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x1f, 0x88, 0x81, 0x35,
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0x78, 0x88, 0x88, 0x85, 0x88, 0x88, 0x88, 0x0f,
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0x88, 0x80, 0x24, 0x68, 0x88, 0x88, 0x84, 0x88,
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0x88, 0x88, 0x23, 0x10, 0x00, 0x00, 0x1c, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x05,
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0xa0, 0x00, 0x00, 0x00, 0x00);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETGAMMA,
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0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38, 0x36,
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0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13, 0x11,
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0x18, 0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38,
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0x36, 0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13,
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0x11, 0x18);
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msleep(60);
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dev_dbg(dev, "Panel init sequence done\n");
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return 0;
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mipi_dsi_msleep(dsi_ctx, 60);
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}
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static int xpp055c272_unprepare(struct drm_panel *panel)
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{
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struct xpp055c272 *ctx = panel_to_xpp055c272(panel);
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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int ret;
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struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
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ret = mipi_dsi_dcs_set_display_off(dsi);
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if (ret < 0)
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dev_err(ctx->dev, "failed to set display off: %d\n", ret);
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mipi_dsi_dcs_enter_sleep_mode(dsi);
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if (ret < 0) {
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dev_err(ctx->dev, "failed to enter sleep mode: %d\n", ret);
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return ret;
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}
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mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
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mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
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if (dsi_ctx.accum_err)
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return dsi_ctx.accum_err;
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regulator_disable(ctx->iovcc);
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regulator_disable(ctx->vci);
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@ -155,17 +144,19 @@ static int xpp055c272_prepare(struct drm_panel *panel)
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{
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struct xpp055c272 *ctx = panel_to_xpp055c272(panel);
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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int ret;
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struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
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dev_dbg(ctx->dev, "Resetting the panel\n");
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ret = regulator_enable(ctx->vci);
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if (ret < 0) {
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dev_err(ctx->dev, "Failed to enable vci supply: %d\n", ret);
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return ret;
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dsi_ctx.accum_err = regulator_enable(ctx->vci);
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if (dsi_ctx.accum_err) {
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dev_err(ctx->dev, "Failed to enable vci supply: %d\n",
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dsi_ctx.accum_err);
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return dsi_ctx.accum_err;
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}
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ret = regulator_enable(ctx->iovcc);
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if (ret < 0) {
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dev_err(ctx->dev, "Failed to enable iovcc supply: %d\n", ret);
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dsi_ctx.accum_err = regulator_enable(ctx->iovcc);
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if (dsi_ctx.accum_err) {
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dev_err(ctx->dev, "Failed to enable iovcc supply: %d\n",
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dsi_ctx.accum_err);
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goto disable_vci;
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}
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@ -177,26 +168,17 @@ static int xpp055c272_prepare(struct drm_panel *panel)
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/* T8: 20ms */
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msleep(20);
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ret = xpp055c272_init_sequence(ctx);
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if (ret < 0) {
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dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret);
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goto disable_iovcc;
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}
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ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
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if (ret < 0) {
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dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret);
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goto disable_iovcc;
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}
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xpp055c272_init_sequence(&dsi_ctx);
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if (!dsi_ctx.accum_err)
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dev_dbg(ctx->dev, "Panel init sequence done\n");
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mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
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/* T9: 120ms */
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msleep(120);
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mipi_dsi_msleep(&dsi_ctx, 120);
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mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
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ret = mipi_dsi_dcs_set_display_on(dsi);
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if (ret < 0) {
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dev_err(ctx->dev, "Failed to set display on: %d\n", ret);
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if (dsi_ctx.accum_err)
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goto disable_iovcc;
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}
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msleep(50);
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@ -206,7 +188,7 @@ static int xpp055c272_prepare(struct drm_panel *panel)
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regulator_disable(ctx->iovcc);
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disable_vci:
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regulator_disable(ctx->vci);
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return ret;
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return dsi_ctx.accum_err;
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}
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static const struct drm_display_mode default_mode = {
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