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Merge "pinctrl: qcom: Add support to set wakeup_enable bit"

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This commit is contained in:
qctecmdr 2022-07-08 18:18:32 -07:00 committed by Gerrit - the friendly Code Review server
commit 80189a228c
3 changed files with 24 additions and 1 deletions
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19
drivers/pinctrl/qcom/pinctrl-msm.c
View File

@ -1317,6 +1317,8 @@ static int msm_gpio_wakeirq(struct gpio_chip *gc,
{
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
const struct msm_gpio_wakeirq_map *map;
const struct msm_pingroup *g;
u32 intr_cfg;
int i;
*parent = GPIO_NO_WAKE_IRQ;
@ -1330,6 +1332,23 @@ static int msm_gpio_wakeirq(struct gpio_chip *gc,
}
}
/*
* Additionally set intr_wakeup_enable_bit for the GPIOs Routed
* to parent irqchip depending on intr_wakeup_present_bit.
*/
if (*parent != GPIO_NO_WAKE_IRQ) {
g = &pctrl->soc->groups[child];
if (!g->intr_wakeup_present_bit)
return 0;
intr_cfg = msm_readl_intr_cfg(pctrl, g);
if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {
intr_cfg |= BIT(g->intr_wakeup_enable_bit);
msm_writel_intr_cfg(intr_cfg, pctrl, g);
}
}
return 0;
}

2
drivers/pinctrl/qcom/pinctrl-msm.h
View File

@ -93,6 +93,8 @@ struct msm_pingroup {
unsigned intr_ack_high:1;
unsigned intr_target_bit:5;
unsigned intr_wakeup_enable_bit:5;
unsigned intr_wakeup_present_bit:5;
unsigned intr_target_kpss_val:5;
unsigned intr_raw_status_bit:5;
unsigned intr_polarity_bit:5;

4
drivers/pinctrl/qcom/pinctrl-pineapple.c
View File

@ -50,7 +50,9 @@
.out_bit = 1, \
.intr_enable_bit = 0, \
.intr_status_bit = 0, \
.intr_target_bit = 5, \
.intr_target_bit = 8, \
.intr_wakeup_enable_bit = 7, \
.intr_wakeup_present_bit = 6, \
.intr_target_kpss_val = 3, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \