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drm/msm/dpu: use full scale alpha in _dpu_crtc_setup_blend_cfg()

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Both _dpu_crtc_setup_blend_cfg() and setup_blend_config_alpha()
callbacks embed knowledge about platform's alpha range (8-bit or
10-bit). Make _dpu_crtc_setup_blend_cfg() use full 16-bit values for
alpha and reduce alpha only in DPU-specific callbacks.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/697898/
Link: https://lore.kernel.org/r/20260112-dpu-rework-alpha-v2-2-d168785911d5@oss.qualcomm.com
This commit is contained in:
Dmitry Baryshkov 2026-01-12 05:23:31 +02:00
parent eef07fd9aa
commit 7fe04c7c43
3 changed files with 19 additions and 20 deletions
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16
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
View File

@ -326,26 +326,20 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
{
struct dpu_hw_mixer *lm = mixer->hw_lm;
u32 blend_op;
u32 fg_alpha, bg_alpha, max_alpha;
u32 fg_alpha, bg_alpha;
if (mdss_ver->core_major_ver < 12) {
max_alpha = 0xff;
fg_alpha = pstate->base.alpha >> 8;
} else {
max_alpha = 0x3ff;
fg_alpha = pstate->base.alpha >> 6;
}
fg_alpha = pstate->base.alpha;
/* default to opaque blending */
if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
!format->alpha_enable) {
blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
DPU_BLEND_BG_ALPHA_BG_CONST;
bg_alpha = max_alpha - fg_alpha;
bg_alpha = DRM_BLEND_ALPHA_OPAQUE - fg_alpha;
} else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
DPU_BLEND_BG_ALPHA_FG_PIXEL;
if (fg_alpha != max_alpha) {
if (fg_alpha != DRM_BLEND_ALPHA_OPAQUE) {
bg_alpha = fg_alpha;
blend_op |= DPU_BLEND_BG_MOD_ALPHA |
DPU_BLEND_BG_INV_MOD_ALPHA;
@ -357,7 +351,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
/* coverage blending */
blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
DPU_BLEND_BG_ALPHA_FG_PIXEL;
if (fg_alpha != max_alpha) {
if (fg_alpha != DRM_BLEND_ALPHA_OPAQUE) {
bg_alpha = fg_alpha;
blend_op |= DPU_BLEND_FG_MOD_ALPHA |
DPU_BLEND_FG_INV_MOD_ALPHA |

21
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
View File

@ -126,7 +126,9 @@ static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)
}
static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx,
u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
u32 stage,
u16 fg_alpha, u16 bg_alpha,
u32 blend_op)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
int stage_off;
@ -139,15 +141,16 @@ static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx
if (WARN_ON(stage_off < 0))
return;
const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16);
const_alpha = (bg_alpha >> 8) | ((fg_alpha >> 8) << 16);
DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha);
DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
}
static void
dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx,
u32 stage, u32 fg_alpha,
u32 bg_alpha, u32 blend_op)
u32 stage,
u16 fg_alpha, u16 bg_alpha,
u32 blend_op)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
int stage_off;
@ -160,13 +163,15 @@ dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx,
if (WARN_ON(stage_off < 0))
return;
const_alpha = (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16);
const_alpha = (bg_alpha >> 6) | ((fg_alpha >> 6) << 16);
DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha);
DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
}
static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx,
u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
u32 stage,
u16 fg_alpha, u16 bg_alpha,
u32 blend_op)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
int stage_off;
@ -178,8 +183,8 @@ static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx,
if (WARN_ON(stage_off < 0))
return;
DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha);
DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha);
DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha >> 8);
DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha >> 8);
DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
}

2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
View File

@ -41,7 +41,7 @@ struct dpu_hw_lm_ops {
* for the specified stage
*/
void (*setup_blend_config)(struct dpu_hw_mixer *ctx, uint32_t stage,
uint32_t fg_alpha, uint32_t bg_alpha, uint32_t blend_op);
u16 fg_alpha, u16 bg_alpha, uint32_t blend_op);
/**
* @setup_alpha_out: Alpha color component selection from either fg or bg