From 7fb197a5cfdb3b549e47b58d10fb252d26e3501f Mon Sep 17 00:00:00 2001
From: Jianqun Xu <jay.xu@rock-chips.com>
Date: Mon, 27 Nov 2017 16:36:16 +0800
Subject: [PATCH] ARM: dts: rockchip: rk312x fix to SCLK_CIF_OUT for cif out
 clk

Change-Id: Id78693129890ddff151753229681b00b911859c9
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
 arch/arm/boot/dts/rk312x.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi
index 6a8cdd6189f2..ba5b49fc09ea 100644
--- a/arch/arm/boot/dts/rk312x.dtsi
+++ b/arch/arm/boot/dts/rk312x.dtsi
@@ -418,7 +418,7 @@ cif: cif@1010a000 {
 		reg = <0x1010a000 0x200>;
 		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>,
-				<&cru SCLK_CIF_SRC>, <&cru SCLK_CIF_OUT_SRC>;
+				<&cru SCLK_CIF_SRC>, <&cru SCLK_CIF_OUT>;
 		clock-names = "aclk_cif0", "hclk_cif0",
 				"cif0_in", "cif0_out";
 		resets = <&cru SRST_CIF0>;