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ARM: dts: rockchip: rk312x fix to SCLK_CIF_OUT for cif out clk
Change-Id: Id78693129890ddff151753229681b00b911859c9 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
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@ -418,7 +418,7 @@ cif: cif@1010a000 {
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reg = <0x1010a000 0x200>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>,
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<&cru SCLK_CIF_SRC>, <&cru SCLK_CIF_OUT_SRC>;
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<&cru SCLK_CIF_SRC>, <&cru SCLK_CIF_OUT>;
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clock-names = "aclk_cif0", "hclk_cif0",
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"cif0_in", "cif0_out";
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resets = <&cru SRST_CIF0>;
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