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https://github.com/torvalds/linux.git
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amd-drm-fixes-7.3-2026-09-03:
amdgpu: - SR-IOV fix - GFX8 fix - MES queue reset fix - GPUVM fixes - DCN 6 warning fix - DCN 3.5/3.6 fix - DML fix - Backlight fix - Colorop fix - DC get_estimated_bw() fix - devcoredump fix - Userq fixes - APU PSP fix - Cursor fix amdkfd: - MES queue eviction fix - MQD debugfs fix UAPI: - Fix for drm_amdgpu_info_device with mixed 64 bit kernel and 32 bit userspace -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQgO5Idg2tXNTSZAr293/aFa7yZ2AUCapmnvwAKCRC93/aFa7yZ 2DbfAQCapkI0p5iRMd/2fk2JcdhhaHfTtwdNEKyiHx7Z8Fyo7wD/egYUpCbhpy4W 6bavqT8G5Gkn4+myqJmD9bIVoWmdlAA= =tJ2Q -----END PGP SIGNATURE----- Merge tag 'amd-drm-fixes-7.3-2026-09-03' of https://gitlab.freedesktop.org/drm/amdgpu/kernel into drm-fixes amd-drm-fixes-7.3-2026-09-03: amdgpu: - SR-IOV fix - GFX8 fix - MES queue reset fix - GPUVM fixes - DCN 6 warning fix - DCN 3.5/3.6 fix - DML fix - Backlight fix - Colorop fix - DC get_estimated_bw() fix - devcoredump fix - Userq fixes - APU PSP fix - Cursor fix amdkfd: - MES queue eviction fix - MQD debugfs fix UAPI: - Fix for drm_amdgpu_info_device with mixed 64 bit kernel and 32 bit userspace Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260903174712.584320-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
commit
7f78fe856e
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@ -299,10 +299,10 @@ amdgpu_devcoredump_print_ibs(struct drm_printer *p,
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amdgpu_res_first(abo->tbo.resource, offset,
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coredump->ibs[i].ib_size_dw * 4, &cursor);
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while (cursor.remaining) {
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amdgpu_device_mm_access(adev, cursor.start / 4,
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&ib_content[off], cursor.size / 4,
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amdgpu_device_mm_access(adev, cursor.start,
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&ib_content[off], cursor.size,
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false);
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off += cursor.size;
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off += cursor.size / 4;
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amdgpu_res_next(&cursor, cursor.size);
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}
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emit_content = true;
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@ -771,6 +771,9 @@ static int amdgpu_device_read_fb_via_bar0(struct amdgpu_device *adev,
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if (!buf || !size)
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return -EINVAL;
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if (!amdgpu_sriov_vf(adev))
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return -EINVAL;
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flags = pci_resource_flags(adev->pdev, 0);
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if ((flags & IORESOURCE_UNSET) || !(flags & IORESOURCE_MEM))
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return -EINVAL;
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@ -879,7 +879,7 @@ bool amdgpu_mes_queue_reset_by_mes_supported(struct amdgpu_device *adev)
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return (ip_maj == 11 && mes_sched >= 0x8c) ||
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((ip_maj == 12 && ip_min == 0) && mes_sched >= 0x8d) ||
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((ip_maj == 12 && ip_min == 1) && mes_sched >= 0x73);
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((ip_maj == 12 && ip_min == 1) && mes_sched >= 0x7b);
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}
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/* Fix me -- node_id is used to identify the correct MES instances in the future */
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@ -396,6 +396,12 @@ static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
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bool ret = false;
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int i;
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/*
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* Runtime DB is for dGPUs only.
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*/
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if (adev->flags & AMD_IS_APU)
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return false;
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if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
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amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
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amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) ||
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@ -1544,7 +1544,7 @@ int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost)
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struct amdgpu_usermode_queue *queue;
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const struct amdgpu_userq_funcs *userq_funcs;
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unsigned long queue_id;
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int r = 0;
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int ret = 0, r;
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xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) {
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if (queue->state == AMDGPU_USERQ_STATE_HUNG && !vram_lost) {
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@ -1555,6 +1555,7 @@ int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost)
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r = userq_funcs->map(queue);
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if (r) {
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dev_err(adev->dev, "Failed to remap queue %ld\n", queue_id);
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ret = r;
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continue;
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}
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trace_amdgpu_userq_state_changed(queue, AMDGPU_USERQ_STATE_MAPPED);
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@ -1562,5 +1563,5 @@ int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost)
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}
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}
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return r;
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return ret;
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}
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@ -2090,7 +2090,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
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after->start = eaddr + 1;
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after->last = tmp->last;
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after->offset = tmp->offset;
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after->offset += (after->start - tmp->start) << PAGE_SHIFT;
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after->offset += (after->start - tmp->start) << AMDGPU_GPU_PAGE_SHIFT;
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after->flags = tmp->flags;
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after->bo_va = tmp->bo_va;
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list_add(&after->list, &tmp->bo_va->invalids);
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@ -3122,7 +3122,7 @@ static void amdgpu_debugfs_vm_bo_status_info(struct seq_file *m,
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id = 0;
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seq_puts(m, "\tIdle BOs:\n");
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list_for_each_entry(base, &lists->needs_update, vm_status) {
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list_for_each_entry(base, &lists->idle, vm_status) {
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if (!base->bo)
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continue;
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@ -1651,10 +1651,10 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
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case IP_VERSION(11, 0, 2):
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case IP_VERSION(11, 0, 3):
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if (!adev->gfx.disable_uq &&
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adev->gfx.me_fw_version >= 2420 &&
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adev->gfx.pfp_fw_version >= 2580 &&
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adev->gfx.mec_fw_version >= 2650 &&
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adev->mes.fw_version[0] >= 120) {
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adev->gfx.me_fw_version >= 3090 &&
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adev->gfx.pfp_fw_version >= 3190 &&
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adev->gfx.mec_fw_version >= 3450 &&
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adev->mes.fw_version[0] >= 147) {
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adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
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adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
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}
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@ -1436,10 +1436,10 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
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case IP_VERSION(12, 0, 0):
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case IP_VERSION(12, 0, 1):
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if (!adev->gfx.disable_uq &&
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adev->gfx.me_fw_version >= 2780 &&
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adev->gfx.pfp_fw_version >= 2840 &&
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adev->gfx.mec_fw_version >= 3050 &&
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adev->mes.fw_version[0] >= 123) {
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adev->gfx.me_fw_version >= 3090 &&
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adev->gfx.pfp_fw_version >= 3190 &&
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adev->gfx.mec_fw_version >= 3450 &&
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adev->mes.fw_version[0] >= 147) {
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adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
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adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
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}
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@ -4546,9 +4546,11 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
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/* set static priority for a queue/ring */
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gfx_v8_0_mqd_set_priority(ring, mqd);
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tmp = RREG32(mmCP_HQD_QUANTUM);
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tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1);
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tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);
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tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 10);
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if (ring != &adev->gfx.kiq[0].ring) {
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tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1);
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tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);
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tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 10);
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}
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mqd->cp_hqd_quantum = tmp;
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/* map_queues packet doesn't need activate the queue,
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@ -1455,6 +1455,14 @@ static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
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dqm_evict_mqd_bo(dqm, q);
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}
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/*
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* Heavy-weight TLB flush after MES removes queues to ensure
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* in-flight memory accesses complete before memory is freed/migrated.
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* HWS does this automatically, MES does not.
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*/
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if (dqm->dev->kfd->shared_resources.enable_mes)
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kfd_flush_tlb(pdd);
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if (!dqm->dev->kfd->shared_resources.enable_mes) {
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pdd->last_evict_timestamp = get_jiffies_64();
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retval = execute_queues_cpsch(dqm,
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@ -3746,8 +3754,11 @@ int suspend_queues(struct kfd_process *p,
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if (!per_device_suspended) {
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dqm_unlock(dqm);
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mutex_unlock(&p->event_mutex);
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if (total_suspended)
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if (total_suspended) {
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amdgpu_amdkfd_debug_mem_fence(dqm->dev->adev);
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/* Heavy-weight TLB flush after MES suspends queues */
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kfd_flush_tlb(pdd);
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}
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continue;
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}
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@ -1169,13 +1169,13 @@ int pqm_debugfs_mqds(struct seq_file *m, void *data)
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mqd_mgr = q->device->dqm->mqd_mgrs[mqd_type];
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size = mqd_mgr->mqd_stride(mqd_mgr,
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&q->properties);
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}
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for (xcc = 0; xcc < num_xccs; xcc++) {
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mqd = q->mqd + size * xcc;
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r = mqd_mgr->debugfs_show_mqd(m, mqd);
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if (r != 0)
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break;
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for (xcc = 0; xcc < num_xccs; xcc++) {
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mqd = q->mqd + size * xcc;
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r = mqd_mgr->debugfs_show_mqd(m, mqd);
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if (r != 0)
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break;
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}
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}
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}
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@ -534,8 +534,12 @@ void amdgpu_dm_update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
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else if (!IS_ERR_OR_NULL(panel_backlight_quirk) &&
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panel_backlight_quirk->force_pwm)
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caps->aux_support = false;
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if (caps->aux_support)
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aconnector->dc_link->backlight_control_type = BACKLIGHT_CONTROL_AMD_AUX;
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if (caps->aux_support) {
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if (aconnector->dc_link->dpcd_caps.panel_luminance_control)
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aconnector->dc_link->backlight_control_type = BACKLIGHT_CONTROL_VESA_AUX;
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else
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aconnector->dc_link->backlight_control_type = BACKLIGHT_CONTROL_AMD_AUX;
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}
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luminance_range = &conn_base->display_info.luminance_range;
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@ -1797,7 +1797,11 @@ bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
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* pipe-split, merge together per same height.
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*/
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for (split_pipe = pipe_ctx->top_pipe; split_pipe;
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split_pipe = split_pipe->top_pipe)
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split_pipe = split_pipe->top_pipe) {
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if (split_pipe == test_pipe)
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continue;
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if (split_pipe->plane_state->layer_index == test_pipe->plane_state->layer_index) {
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struct rect r2_half;
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@ -1809,6 +1813,7 @@ bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
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r2_bottom = min(r2_bottom, r2_half.y + r2_half.height);
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break;
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}
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}
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if (r1.x >= r2.x && r1.y >= r2.y && r1_right <= r2_right && r1_bottom <= r2_bottom)
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return true;
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@ -320,6 +320,8 @@ static struct fixed31_32 interp_tf_pts(const struct fixed31_32 *output_tf_channe
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return value;
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}
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#define NUM_DEGAMMA_REGIONS 9
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bool cm3_helper_translate_curve_to_degamma_hw_format(
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const struct dc_transfer_func *output_tf,
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struct pwl_params *lut_params)
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@ -343,31 +345,15 @@ bool cm3_helper_translate_curve_to_degamma_hw_format(
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memset(lut_params, 0, sizeof(struct pwl_params));
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memset(seg_distr, 0, sizeof(seg_distr));
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if (output_tf->tf == TRANSFER_FUNCTION_PQ ||
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output_tf->tf == TRANSFER_FUNCTION_SRGB) {
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/* 9 segments
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* segments are from 2^-9 to 0
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*/
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const uint8_t SEG_COUNT = 9;
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seg_distr[0] = 0; // Since we only have one point in darkest region
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for (k = 1; k < SEG_COUNT; k++)
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seg_distr[k] = k - 1; // 2^(k-1) points per region; halves as k decreases
|
||||
/* 9 segments
|
||||
* segments are from 2^-9 to 2^0
|
||||
*/
|
||||
seg_distr[0] = 0; // Since we only have one point in darkest region
|
||||
for (k = 1; k < NUM_DEGAMMA_REGIONS; k++)
|
||||
seg_distr[k] = k - 1; // 2^(k-1) points per region; halves as k decreases
|
||||
|
||||
region_start = -SEG_COUNT;
|
||||
region_end = 0;
|
||||
} else {
|
||||
/* 12 segments
|
||||
* segments are from 2^-12 to 2^0
|
||||
* There are less than 256 points, for optimization
|
||||
*/
|
||||
const uint8_t SEG_COUNT = 12;
|
||||
|
||||
for (i = 0; i < SEG_COUNT; i++)
|
||||
seg_distr[i] = 4;
|
||||
|
||||
region_start = -SEG_COUNT;
|
||||
region_end = 0;
|
||||
}
|
||||
region_start = -NUM_DEGAMMA_REGIONS;
|
||||
region_end = 0;
|
||||
|
||||
for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
|
||||
seg_distr[i] = -1;
|
||||
|
|
|
|||
|
|
@ -1128,8 +1128,8 @@ static bool dcn5_mode_programming(struct dml2_core_calcs_mode_programming_ex *in
|
|||
CalculateWatermarks_params->USRRetrainingSupport = &mode_lib->mp.USRRetrainingSupport;
|
||||
CalculateWatermarks_params->temp_read_or_ppt_support = mode_lib->mp.temp_read_or_ppt_support;
|
||||
CalculateWatermarks_params->global_temp_read_or_ppt_supported = &mode_lib->mp.global_temp_read_or_ppt_supported;
|
||||
CalculateWatermarks_params->VActiveLatencyHidingMargin = 0;
|
||||
CalculateWatermarks_params->VActiveLatencyHidingUs = 0;
|
||||
CalculateWatermarks_params->VActiveLatencyHidingMargin = NULL;
|
||||
CalculateWatermarks_params->VActiveLatencyHidingUs = NULL;
|
||||
|
||||
dcn5_calculate_watermarks_and_dram_speed_change_support(&mode_lib->scratch, CalculateWatermarks_params);
|
||||
|
||||
|
|
|
|||
|
|
@ -1819,8 +1819,8 @@ struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_param
|
|||
bool UnboundedRequestEnabled;
|
||||
unsigned int CompressedBufferSizeInkByte;
|
||||
bool max_outstanding_when_urgent_expected;
|
||||
const unsigned int max_outstanding_requests;
|
||||
const unsigned int max_request_size_bytes;
|
||||
unsigned int max_outstanding_requests;
|
||||
unsigned int max_request_size_bytes;
|
||||
const unsigned int *meta_row_height_l;
|
||||
const unsigned int *meta_row_height_c;
|
||||
const enum dml2_pstate_method *uclk_pstate_switch_modes;
|
||||
|
|
|
|||
|
|
@ -1414,7 +1414,7 @@ static bool find_shift_for_valid_cache_id_assignment(const int *mcache_boundarie
|
|||
success = true;
|
||||
for (pipe_index = 0; pipe_index < pipe_count; pipe_index++) {
|
||||
if (!calculate_first_second_splitting(mcache_boundaries, num_boundaries, *shift,
|
||||
pipe_vp_startx[pipe_index], pipe_vp_endx[pipe_index], 0, 0)) {
|
||||
pipe_vp_startx[pipe_index], pipe_vp_endx[pipe_index], NULL, NULL)) {
|
||||
success = false;
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -301,6 +301,7 @@ void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, s
|
|||
out->smn_latency_us = 2;
|
||||
out->dispclk_dppclk_vco_speed_mhz = 3600;
|
||||
out->pct_ideal_dram_bw_after_urgent_pixel_only = 65.0;
|
||||
out->gpuvm_min_page_size_kbytes = 4;
|
||||
break;
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -103,6 +103,11 @@ static int get_estimated_bw(struct dc_link *link)
|
|||
{
|
||||
uint8_t bw_estimated_bw = 0;
|
||||
|
||||
if (link->dpia_bw_alloc_config.bw_granularity == 0) {
|
||||
DC_LOG_ERROR("%s: BW granularity is zero!\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
core_link_read_dpcd(
|
||||
link,
|
||||
ESTIMATED_BW,
|
||||
|
|
|
|||
|
|
@ -1512,6 +1512,7 @@ struct drm_amdgpu_info_device {
|
|||
__u64 high_va_max;
|
||||
/* gfx10 pa_sc_tile_steering_override */
|
||||
__u32 pa_sc_tile_steering_override;
|
||||
__u32 pad;
|
||||
/* disabled TCCs */
|
||||
__u64 tcc_disabled_mask;
|
||||
__u64 min_engine_clock;
|
||||
|
|
@ -1536,7 +1537,6 @@ struct drm_amdgpu_info_device {
|
|||
__u32 csa_alignment;
|
||||
/* Userq IP mask (1 << AMDGPU_HW_IP_*) */
|
||||
__u32 userq_ip_mask;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_hw_ip {
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user