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drm/xe: Implement HW workaround 14016763929
To workaround a HW bug on DG2, driver is required to map the whole
ppgtt virtual address space before GPU workload submission. Thus
set the XE_VM_FLAG_SCRATCH_PAGE flag during vm create so the whole
address space is mapped to point to scratch page.
v1:
- Move the workaround implementation from xe_vm_create to
xe_vm_create_ioctl - Brian
- Reorder error checking in xe_vm_create_ioctl - Jose
- Implement WA only for DG2-G10 and DG2-G12
Signed-off-by: Oak Zeng <oak.zeng@intel.com>
Reviewed-by: Brian Welty <brian.welty@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
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@ -40,7 +40,7 @@ quiet_cmd_wa_oob = GEN $(notdir $(generated_oob))
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$(generated_oob) &: $(obj)/xe_gen_wa_oob $(srctree)/$(src)/xe_wa_oob.rules
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$(call cmd,wa_oob)
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$(obj)/xe_guc.o $(obj)/xe_wa.o $(obj)/xe_ring_ops.o: $(generated_oob)
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$(obj)/xe_guc.o $(obj)/xe_wa.o $(obj)/xe_ring_ops.o $(obj)/xe_vm.o: $(generated_oob)
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# Please keep these build lists sorted!
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@ -29,6 +29,8 @@
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#include "xe_res_cursor.h"
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#include "xe_sync.h"
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#include "xe_trace.h"
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#include "generated/xe_wa_oob.h"
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#include "xe_wa.h"
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#define TEST_VM_ASYNC_OPS_ERROR
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@ -1979,6 +1981,13 @@ int xe_vm_create_ioctl(struct drm_device *dev, void *data,
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int err;
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u32 flags = 0;
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if (XE_WA(xe_root_mmio_gt(xe), 14016763929))
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args->flags |= DRM_XE_VM_CREATE_SCRATCH_PAGE;
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if (XE_IOCTL_DBG(xe, args->flags & DRM_XE_VM_CREATE_FAULT_MODE &&
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!xe->info.supports_usm))
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return -EINVAL;
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if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
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return -EINVAL;
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@ -2001,10 +2010,6 @@ int xe_vm_create_ioctl(struct drm_device *dev, void *data,
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xe_device_in_fault_mode(xe)))
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return -EINVAL;
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if (XE_IOCTL_DBG(xe, args->flags & DRM_XE_VM_CREATE_FAULT_MODE &&
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!xe->info.supports_usm))
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return -EINVAL;
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if (args->flags & DRM_XE_VM_CREATE_SCRATCH_PAGE)
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flags |= XE_VM_FLAG_SCRATCH_PAGE;
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if (args->flags & DRM_XE_VM_CREATE_COMPUTE_MODE)
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@ -15,3 +15,5 @@
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18020744125 PLATFORM(PVC)
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1509372804 PLATFORM(PVC), GRAPHICS_STEP(A0, C0)
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1409600907 GRAPHICS_VERSION_RANGE(1200, 1250)
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14016763929 SUBPLATFORM(DG2, G10)
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SUBPLATFORM(DG2, G12)
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