From b6488fc692ebd719e06e4323aa08e67541ad2d77 Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Wed, 31 Aug 2022 11:53:09 -0700 Subject: [PATCH 1/2] clk: qcom: camcc-pineapple: Remove BOOT_CRITICAL from some clocks The core_ahb and cpas_ahb clocks aren't critical during kernel boot. Only the drv_ahb and drv_xo clocks are, since those are the only ones required for the cam_rsc device to access its registers while probing. The core_ahb and cpas_ahb clocks require the titan_top_gdsc to be enabled, which isn't the case during camcc probe, so trying to enable them results in "stuck off" warnings. Change-Id: I95c19150f4812996737fffa29ac974f133bef92e Signed-off-by: Mike Tipton --- drivers/clk/qcom/camcc-pineapple.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/qcom/camcc-pineapple.c b/drivers/clk/qcom/camcc-pineapple.c index 7227e06f39f2..fb8a952c20be 100644 --- a/drivers/clk/qcom/camcc-pineapple.c +++ b/drivers/clk/qcom/camcc-pineapple.c @@ -2318,7 +2318,6 @@ static struct clk_branch cam_cc_core_ahb_clk = { .clkr = { .enable_reg = 0x132d0, .enable_mask = BIT(0), - .flags = QCOM_CLK_BOOT_CRITICAL, .hw.init = &(const struct clk_init_data){ .name = "cam_cc_core_ahb_clk", .parent_hws = (const struct clk_hw*[]){ @@ -2337,7 +2336,6 @@ static struct clk_branch cam_cc_cpas_ahb_clk = { .clkr = { .enable_reg = 0x13220, .enable_mask = BIT(0), - .flags = QCOM_CLK_BOOT_CRITICAL, .hw.init = &(const struct clk_init_data){ .name = "cam_cc_cpas_ahb_clk", .parent_hws = (const struct clk_hw*[]){ From d5419b1de959eaff74881454df36bfed7b747dac Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Wed, 31 Aug 2022 11:57:52 -0700 Subject: [PATCH 2/2] clk: qcom: clk-alpha-pll: Only configure lucid_evo outputs once Which outputs are enabled when PLL_OUTCTRL is asserted only need to be configured once. When PLL_OUTCTRL is 0 then all the outputs are disabled anyway. There's no need to enable/disable the individual outputs each time the PLL is toggled. Additionally, in some cases PLLs may be enabled from bootloaders without all the outputs enabled that we intend to use. In which case we still need to enable the required outputs during initial configuration even if the PLL is already on. Enabling additional outputs when the PLL is already running is safe. Change-Id: Iffa471783ed5021a92f31673fb2e7539741973b9 Signed-off-by: Mike Tipton --- drivers/clk/qcom/clk-alpha-pll.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 74ef4b136a65..79f15e28481f 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2015, 2018-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -3009,6 +3009,10 @@ int clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, { int ret; + ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); + if (ret) + return ret; + ret = trion_pll_is_enabled(pll, regmap); if (ret) return ret; @@ -3130,11 +3134,6 @@ static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) if (ret) return ret; - /* Enable the PLL outputs */ - ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); - if (ret) - return ret; - /* Enable the global PLL outputs */ ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); if (ret) @@ -3167,11 +3166,6 @@ static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) if (ret) return; - /* Disable the PLL outputs */ - ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); - if (ret) - return; - /* Place the PLL mode in STANDBY */ regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);