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dmaengine: xilinx_dma: Fix hardware buffer descriptor chain after cyclic DMA

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Using the DMA in cyclic mode modifies the hardware buffer descriptor
chain in xilinx_dma_prep_dma_cyclic so that the last descriptor used by
the cyclic transfer points back to the first descriptor, but it never
restores the original descriptor ring. This breaks using non-cyclic mode
after cyclic mode with an error like:

  xilinx-vdma 86000000.dma: Channel 00000000354d5c8d has errors 100, cdr 6de40000 tdr 6de40400

The only way to get out of this error state is to rebuild the hardware
buffer descriptor ring by releasing and re-acquiring the channel.

Fix using non-cyclic mode after cyclic mode by always restoring the
original buffer descriptor ring in the same manner as it is set up by
xilinx_dma_alloc_chan_resources().

Fixes: 23059408b6 ("dmaengine: xilinx_dma: Fix race condition in the driver for multiple descriptor scenario")
Signed-off-by: Alex Bereza <alex@bereza.email>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Suraj Gupta <suraj.gupta2@amd.com>
Link: https://patch.msgid.link/20260817-fix-hw-buf-desc-after-cyclic-mode-v1-1-1fe47e701d6c@bereza.email
Link: https://patch.msgid.link/20260818-fix-hw-buf-desc-after-cyclic-mode-v2-1-530ff44c6a81@bereza.email
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Alex Bereza 2026-08-18 09:36:29 +02:00 committed by Vinod Koul
parent f6504be006
commit 7ed1e3070c
1 changed files with 17 additions and 7 deletions
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24
drivers/dma/xilinx/xilinx_dma.c
View File

@ -756,15 +756,25 @@ xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
return segment;
}
static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw)
static void xilinx_dma_clean_hw_desc(struct xilinx_dma_chan *chan,
struct xilinx_axidma_tx_segment *segment)
{
u32 next_desc = hw->next_desc;
u32 next_desc_msb = hw->next_desc_msb;
dma_addr_t next;
u32 i;
memset(hw, 0, sizeof(struct xilinx_axidma_desc_hw));
/*
* Restore the buffer descriptor's next descriptor pointer to the value
* set up in xilinx_dma_alloc_chan_resources(). Otherwise using the DMA
* in cyclic mode leaves the next descriptor pointer altered and
* prevents subsequent non-cyclic transfers.
*/
i = segment - chan->seg_v;
next = chan->seg_p +
sizeof(*chan->seg_v) * ((i + 1) % XILINX_DMA_NUM_DESCS);
hw->next_desc = next_desc;
hw->next_desc_msb = next_desc_msb;
memset(&segment->hw, 0, sizeof(segment->hw));
segment->hw.next_desc = lower_32_bits(next);
segment->hw.next_desc_msb = upper_32_bits(next);
}
static void xilinx_mcdma_clean_hw_desc(struct xilinx_aximcdma_desc_hw *hw)
@ -786,7 +796,7 @@ static void xilinx_mcdma_clean_hw_desc(struct xilinx_aximcdma_desc_hw *hw)
static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan,
struct xilinx_axidma_tx_segment *segment)
{
xilinx_dma_clean_hw_desc(&segment->hw);
xilinx_dma_clean_hw_desc(chan, segment);
list_add_tail(&segment->node, &chan->free_seg_list);
}