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iio: adc: ad7768-1: Ensure SYNC_IN pulse minimum timing requirement

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The SYNC_IN pulse width must be at least 1.5 x Tmclk, corresponding to
~2.5 µs at the lowest supported MCLK frequency. Add a 3 µs delay to
ensure reliable synchronization timing even for the worst-case scenario.

Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com>
Reviewed-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/d3ee92a533cd1207cf5c5cc4d7bdbb5c6c267f68.1749063024.git.Jonathan.Santos@analog.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Jonathan Santos 2025-06-04 16:35:21 -03:00 committed by Jonathan Cameron
parent a238572b90
commit 7e54d93287
1 changed files with 19 additions and 4 deletions
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23
drivers/iio/adc/ad7768-1.c
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@ -252,6 +252,24 @@ static const struct regmap_config ad7768_regmap24_config = {
.max_register = AD7768_REG24_COEFF_DATA,
};
static int ad7768_send_sync_pulse(struct ad7768_state *st)
{
/*
* The datasheet specifies a minimum SYNC_IN pulse width of 1.5 × Tmclk,
* where Tmclk is the MCLK period. The supported MCLK frequencies range
* from 0.6 MHz to 17 MHz, which corresponds to a minimum SYNC_IN pulse
* width of approximately 2.5 µs in the worst-case scenario (0.6 MHz).
*
* Add a delay to ensure the pulse width is always sufficient to
* trigger synchronization.
*/
gpiod_set_value_cansleep(st->gpio_sync_in, 1);
fsleep(3);
gpiod_set_value_cansleep(st->gpio_sync_in, 0);
return 0;
}
static int ad7768_set_mode(struct ad7768_state *st,
enum ad7768_conv_mode mode)
{
@ -339,10 +357,7 @@ static int ad7768_set_dig_fil(struct ad7768_state *st,
return ret;
/* A sync-in pulse is required every time the filter dec rate changes */
gpiod_set_value(st->gpio_sync_in, 1);
gpiod_set_value(st->gpio_sync_in, 0);
return 0;
return ad7768_send_sync_pulse(st);
}
static int ad7768_set_freq(struct ad7768_state *st,