From 7e47fe56415847732419ca8cef9307bf111dd368 Mon Sep 17 00:00:00 2001 From: Paul Louvel Date: Wed, 8 Jul 2026 12:15:14 +0200 Subject: [PATCH] soc: fsl: qe: Add chained_irq_{enter,exit}() calls in cascade handler Wrap the cascade handler body with chained_irq_{enter,exit}() to properly inform the parent IRQ chip that a chained interrupt is being serviced. Fixes: f0bcd784e1b76 ("soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports") Signed-off-by: Paul Louvel Cc: stable@kernel.org Reviewed-by: Christophe Leroy (CS GROUP) Link: https://lore.kernel.org/r/20260708-qe-pic-gpios-v2-1-1972044cfbd1@bootlin.com Signed-off-by: Christophe Leroy (CS GROUP) --- drivers/soc/fsl/qe/qe_ports_ic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/soc/fsl/qe/qe_ports_ic.c b/drivers/soc/fsl/qe/qe_ports_ic.c index 33ca1ddafe18..c3768c82a58c 100644 --- a/drivers/soc/fsl/qe/qe_ports_ic.c +++ b/drivers/soc/fsl/qe/qe_ports_ic.c @@ -6,6 +6,7 @@ */ #include +#include #include #include @@ -82,7 +83,13 @@ static int qepic_get_irq(struct irq_desc *desc) static void qepic_cascade(struct irq_desc *desc) { + struct irq_chip *chip = irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); + generic_handle_irq(qepic_get_irq(desc)); + + chained_irq_exit(chip, desc); } static int qepic_host_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw)