From 2bae46e3de2a64fe3a619d61b16da0c01b8df2a1 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Wed, 19 Feb 2025 15:02:37 +0100 Subject: [PATCH 1/3] riscv: dts: thead: Introduce power domain nodes with aon firmware The DRM Imagination GPU requires a power-domain driver. In the T-HEAD TH1520 SoC implements power management capabilities through the E902 core, which can be communicated with through the mailbox, using firmware protocol. Add AON node, which servers as a power-domain controller. Signed-off-by: Michal Wilczynski Reviewed-by: Drew Fustini Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 527336417765..fa7985e89d45 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { compatible = "thead,th1520"; @@ -229,6 +230,13 @@ stmmac_axi_config: stmmac-axi-config { snps,blen = <0 0 64 32 0 0 0>; }; + aon: aon { + compatible = "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + #power-domain-cells = <1>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; From 1b136de08b5feca37ebdb6d28db3c9c6285aba5a Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Fri, 25 Apr 2025 11:20:44 -0700 Subject: [PATCH 2/3] riscv: dts: thead: Introduce reset controller node T-HEAD TH1520 SoC requires to put the GPU out of the reset state as part of the power-up sequence. Link: https://lore.kernel.org/linux-riscv/81e53e3a-5873-44c7-9070-5596021daa42@samsung.com/ Reviewed-by: Drew Fustini Signed-off-by: Michal Wilczynski [drew: remove hunk that included thead,th1520-reset.h] Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index fa7985e89d45..32ef846d569c 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -497,6 +497,12 @@ clk: clock-controller@ffef010000 { #clock-cells = <1>; }; + rst: reset-controller@ffef528000 { + compatible = "thead,th1520-reset"; + reg = <0xff 0xef528000 0x0 0x4f>; + #reset-cells = <1>; + }; + dmac0: dma-controller@ffefc00000 { compatible = "snps,axi-dma-1.01a"; reg = <0xff 0xefc00000 0x0 0x1000>; From a4c95b924d513728df8631471eb3b1c300909e21 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 3 Apr 2025 11:44:25 +0200 Subject: [PATCH 3/3] riscv: dts: thead: Add device tree VO clock controller VO clocks reside in a different address space from the AP clocks on the T-HEAD SoC. Add the device tree node of a clock-controller to handle VO address space as well. Reviewed-by: Drew Fustini Signed-off-by: Michal Wilczynski Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 32ef846d569c..1db0054c4e09 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -503,6 +503,13 @@ rst: reset-controller@ffef528000 { #reset-cells = <1>; }; + clk_vo: clock-controller@ffef528050 { + compatible = "thead,th1520-clk-vo"; + reg = <0xff 0xef528050 0x0 0xfb0>; + clocks = <&clk CLK_VIDEO_PLL>; + #clock-cells = <1>; + }; + dmac0: dma-controller@ffefc00000 { compatible = "snps,axi-dma-1.01a"; reg = <0xff 0xefc00000 0x0 0x1000>;