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drm/i915/gt: add wait on depth stall done bit handling

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Add writing of WAIT_ON_DEPTH_STALL_DONE_DISABLE for gen12, this
is performance optimization.

Bspec: 46132

Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12411
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214155712.2849848-2-juhapekka.heikkila@gmail.com
This commit is contained in:
Juha-Pekka Heikkila 2025-02-14 17:57:11 +02:00 committed by Andi Shyti
parent 3a79e5a8b4
commit 7ded94bd11
2 changed files with 9 additions and 0 deletions
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3
drivers/gpu/drm/i915/gt/intel_gt_regs.h
View File

@ -409,6 +409,9 @@
#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
#define GEN8_WM_CHICKEN2 MCR_REG(0x5584)
#define WAIT_ON_DEPTH_STALL_DONE_DISABLE REG_BIT(5)
#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)

6
drivers/gpu/drm/i915/gt/intel_workarounds.c
View File

@ -742,6 +742,12 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
/* Wa_1606376872 */
wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC);
}
/*
* This bit must be set to enable performance optimization for fast
* clears.
*/
wa_mcr_write_or(wal, GEN8_WM_CHICKEN2, WAIT_ON_DEPTH_STALL_DONE_DISABLE);
}
static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,