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drm/amd/display: Update DCN10 resource

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Update DCN10 to use legacy fast update and ensure that the MPCC count is
the same as the pipe_count.

Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rodrigo Siqueira 2024-03-26 11:48:40 -06:00 committed by Alex Deucher
parent 9c78dc956a
commit 7dc363e662
1 changed files with 2 additions and 0 deletions
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drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
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@ -569,6 +569,7 @@ static const struct dc_debug_options debug_defaults_diags = {
.disable_pplib_clock_request = true,
.disable_pplib_wm_range = true,
.underflow_assert_delay_us = 0xFFFFFFFF,
.enable_legacy_fast_update = true,
};
static void dcn10_dpp_destroy(struct dpp **dpp)
@ -1631,6 +1632,7 @@ static bool dcn10_resource_construct(
/* valid pipe num */
pool->base.pipe_count = j;
pool->base.timing_generator_count = j;
pool->base.mpcc_count = j;
/* within dml lib, it is hard code to 4. If ASIC pipe is fused,
* the value may be changed