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PCI: qcom: Add support for Qualcomm SA8255p based PCIe Root Complex
Add functionality to enable resource management (like clocks, regulators, PHY) through firmware and enumerate ECAM compliant Root Complex on SA8255p SoC, where the PCIe Root Complex is firmware managed and configured into ECAM compliant mode. Signed-off-by: Mayank Rana <mayank.rana@oss.qualcomm.com> [mani: minor code cleanups and commit message rewording] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: add "ECAM" in comment] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20250616224259.3549811-5-mayank.rana@oss.qualcomm.com
This commit is contained in:
Mayank Rana
Bjorn Helgaas
parent
d7c7c051e8
commit
7d944c0f14
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@ -296,6 +296,7 @@ config PCIE_QCOM
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select PCIE_DW_HOST
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select CRC8
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select PCIE_QCOM_COMMON
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select PCI_HOST_COMMON
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help
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Say Y here to enable PCIe controller support on Qualcomm SoCs. The
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PCIe controller uses the DesignWare core plus Qualcomm-specific
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@ -21,7 +21,9 @@
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#include <linux/limits.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/pci-ecam.h>
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#include <linux/pm_opp.h>
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#include <linux/pm_runtime.h>
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#include <linux/platform_device.h>
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@ -34,6 +36,7 @@
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#include <linux/units.h>
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#include "../../pci.h"
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#include "../pci-host-common.h"
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#include "pcie-designware.h"
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#include "pcie-qcom-common.h"
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@ -255,10 +258,12 @@ struct qcom_pcie_ops {
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* @ops: qcom PCIe ops structure
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* @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache
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* snooping
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* @firmware_managed: Set if the Root Complex is firmware managed
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*/
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struct qcom_pcie_cfg {
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const struct qcom_pcie_ops *ops;
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bool override_no_snoop;
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bool firmware_managed;
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bool no_l0s;
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};
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@ -1426,6 +1431,10 @@ static const struct qcom_pcie_cfg cfg_sc8280xp = {
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.no_l0s = true,
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};
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static const struct qcom_pcie_cfg cfg_fw_managed = {
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.firmware_managed = true,
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};
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static const struct dw_pcie_ops dw_pcie_ops = {
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.link_up = qcom_pcie_link_up,
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.start_link = qcom_pcie_start_link,
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@ -1579,6 +1588,49 @@ static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data)
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return IRQ_HANDLED;
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}
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static void qcom_pci_free_msi(void *ptr)
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{
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struct dw_pcie_rp *pp = (struct dw_pcie_rp *)ptr;
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if (pp && pp->has_msi_ctrl)
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dw_pcie_free_msi(pp);
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}
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static int qcom_pcie_ecam_host_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct dw_pcie_rp *pp;
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struct dw_pcie *pci;
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int ret;
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pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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if (!pci)
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return -ENOMEM;
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pci->dev = dev;
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pp = &pci->pp;
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pci->dbi_base = cfg->win;
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pp->num_vectors = MSI_DEF_NUM_VECTORS;
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ret = dw_pcie_msi_host_init(pp);
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if (ret)
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return ret;
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pp->has_msi_ctrl = true;
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dw_pcie_msi_init(pp);
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return devm_add_action_or_reset(dev, qcom_pci_free_msi, pp);
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}
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static const struct pci_ecam_ops pci_qcom_ecam_ops = {
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.init = qcom_pcie_ecam_host_init,
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.pci_ops = {
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.map_bus = pci_ecam_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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}
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};
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static int qcom_pcie_probe(struct platform_device *pdev)
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{
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const struct qcom_pcie_cfg *pcie_cfg;
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@ -1593,24 +1645,62 @@ static int qcom_pcie_probe(struct platform_device *pdev)
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char *name;
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pcie_cfg = of_device_get_match_data(dev);
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if (!pcie_cfg || !pcie_cfg->ops) {
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dev_err(dev, "Invalid platform data\n");
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return -EINVAL;
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if (!pcie_cfg) {
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dev_err(dev, "No platform data\n");
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return -ENODATA;
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}
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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if (!pci)
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return -ENOMEM;
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if (!pcie_cfg->firmware_managed && !pcie_cfg->ops) {
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dev_err(dev, "No platform ops\n");
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return -ENODATA;
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}
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pm_runtime_enable(dev);
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ret = pm_runtime_get_sync(dev);
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if (ret < 0)
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goto err_pm_runtime_put;
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if (pcie_cfg->firmware_managed) {
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struct pci_host_bridge *bridge;
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struct pci_config_window *cfg;
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bridge = devm_pci_alloc_host_bridge(dev, 0);
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if (!bridge) {
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ret = -ENOMEM;
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goto err_pm_runtime_put;
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}
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/* Parse and map our ECAM configuration space area */
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cfg = pci_host_common_ecam_create(dev, bridge,
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&pci_qcom_ecam_ops);
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if (IS_ERR(cfg)) {
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ret = PTR_ERR(cfg);
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goto err_pm_runtime_put;
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}
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bridge->sysdata = cfg;
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bridge->ops = (struct pci_ops *)&pci_qcom_ecam_ops.pci_ops;
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bridge->msi_domain = true;
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ret = pci_host_probe(bridge);
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if (ret)
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goto err_pm_runtime_put;
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return 0;
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}
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie) {
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ret = -ENOMEM;
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goto err_pm_runtime_put;
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}
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pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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if (!pci) {
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ret = -ENOMEM;
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goto err_pm_runtime_put;
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}
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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pp = &pci->pp;
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@ -1756,9 +1846,13 @@ static int qcom_pcie_probe(struct platform_device *pdev)
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static int qcom_pcie_suspend_noirq(struct device *dev)
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{
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struct qcom_pcie *pcie = dev_get_drvdata(dev);
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struct qcom_pcie *pcie;
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int ret = 0;
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pcie = dev_get_drvdata(dev);
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if (!pcie)
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return 0;
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/*
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* Set minimum bandwidth required to keep data path functional during
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* suspend.
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@ -1812,9 +1906,13 @@ static int qcom_pcie_suspend_noirq(struct device *dev)
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static int qcom_pcie_resume_noirq(struct device *dev)
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{
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struct qcom_pcie *pcie = dev_get_drvdata(dev);
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struct qcom_pcie *pcie;
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int ret;
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pcie = dev_get_drvdata(dev);
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if (!pcie)
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return 0;
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if (pm_suspend_target_state != PM_SUSPEND_MEM) {
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ret = icc_enable(pcie->icc_cpu);
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if (ret) {
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@ -1849,6 +1947,7 @@ static const struct of_device_id qcom_pcie_match[] = {
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{ .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 },
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{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
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{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
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{ .compatible = "qcom,pcie-sa8255p", .data = &cfg_fw_managed },
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{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
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{ .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_34_0},
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{ .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
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