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MediaTek driver updates for v6.15

Browse Source 
This adds entries for new and missing SoCs in the MediaTek SoCInfo
 driver (MT8370AV/AZA, MT8390AV/AZA) and	an extra entry for a new
 revision of the	MT8395AV/ZA SoC.
 
 The MediaTek SoCInfo driver also gets its SoC attribute	information
 restructured: now the family, machine and soc_id fields are correctly
 populated.
 
 MT8188 gains support for the secondary Display Parallel Interface
 used for HDMI, and for the Display Stream Compression component
 routing through mmsys and mutex tables.
 
 All of the MMSYS drivers get an important overhaul: it was found that,
 in multiple cases, the tables contained wrong mask/value pairs, hence
 those were doing either nothing or breaking routings.
 The mmsys tables were converted to use a newly introduced macro that
 will perform a compile time check, making sure that each table entry's
 value fits in the declared register mask.
 
 Thanks to the new macro, multiple MediaTek SoCs got multiple fixes in
 their MMSYS tables, addressing issues that were severely impacting the
 functionality of the display controller pipelines.
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Merge tag 'mtk-soc-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers

MediaTek driver	updates for v6.15

This adds entries for new and missing SoCs in the MediaTek SoCInfo
driver (MT8370AV/AZA, MT8390AV/AZA) and	an extra entry for a new
revision of the	MT8395AV/ZA SoC.

The MediaTek SoCInfo driver also gets its SoC attribute	information
restructured: now the family, machine and soc_id fields are correctly
populated.

MT8188 gains support for the secondary Display Parallel Interface
used for HDMI, and for the Display Stream Compression component
routing through mmsys and mutex tables.

All of the MMSYS drivers get an important overhaul: it was found that,
in multiple cases, the tables contained wrong mask/value pairs, hence
those were doing either nothing or breaking routings.
The mmsys tables were converted to use a newly introduced macro that
will perform a compile time check, making sure that each table entry's
value fits in the declared register mask.

Thanks to the new macro, multiple MediaTek SoCs got multiple fixes in
their MMSYS tables, addressing issues that were severely impacting the
functionality of the display controller pipelines.

* tag 'mtk-soc-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
  soc: mediatek: mtk-socinfo: Add extra entry for MT8395AV/ZA Genio 1200
  soc: mediatek: mt8188-mmsys: Add support for DSC on VDO0
  soc: mediatek: mmsys: Migrate all tables to MMSYS_ROUTE() macro
  soc: mediatek: mt8365-mmsys: Fix routing table masks and values
  soc: mediatek: mt8167-mmsys: Fix missing regval in all entries
  soc: mediatek: mt8188-mmsys: Migrate to MMSYS_ROUTE() macro
  soc: mediatek: mtk-mmsys: Add compile time check for mmsys routes
  soc: mediatek: mtk-mmsys: Fix MT8188 VDO1 DPI1 output selection
  soc: mediatek: mtk-mutex: Add DPI1 SOF/EOF to MT8188 mutex tables
  soc: mediatek: mtk-socinfo: Avoid using machine attribute in SoC detection log
  soc: mediatek: mtk-socinfo: Add entry for MT8390AV/AZA Genio 700
  soc: mediatek: mtk-socinfo: Add entry for MT8370AV/AZA Genio 510
  soc: mediatek: mtk-socinfo: Restructure SoC attribute information

Link: https://lore.kernel.org/r/20250306113540.148342-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-03-06 17:22:07 +01:00
commit 7d5a549a08
11 changed files with 597 additions and 766 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
drivers/soc/mediatek/mt8167-mmsys.h
View File

@ -14,22 +14,21 @@
#define MT8167_DSI0_SEL_IN_RDMA0 0x1
static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0
},
MMSYS_ROUTE(OVL0, COLOR0,
MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
OVL0_MOUT_EN_COLOR0),
MMSYS_ROUTE(DITHER0, RDMA0,
MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0,
MT8167_DITHER_MOUT_EN_RDMA0),
MMSYS_ROUTE(OVL0, COLOR0,
MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
COLOR0_SEL_IN_OVL0),
MMSYS_ROUTE(RDMA0, DSI0,
MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0,
MT8167_DSI0_SEL_IN_RDMA0),
MMSYS_ROUTE(RDMA0, DSI0,
MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0,
MT8167_RDMA0_SOUT_DSI0),
};
#endif /* __SOC_MEDIATEK_MT8167_MMSYS_H */

99
drivers/soc/mediatek/mt8173-mmsys.h
View File

@ -33,63 +33,48 @@
#define MT8173_RDMA0_SOUT_COLOR0 BIT(0)
static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
MT8173_OVL0_MOUT_EN_COLOR0, MT8173_OVL0_MOUT_EN_COLOR0
}, {
DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN,
MT8173_OD0_MOUT_EN_RDMA0, MT8173_OD0_MOUT_EN_RDMA0
}, {
DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN,
MT8173_UFOE_MOUT_EN_DSI0, MT8173_UFOE_MOUT_EN_DSI0
}, {
DDP_COMPONENT_COLOR0, DDP_COMPONENT_AAL0,
MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN,
MT8173_COLOR0_SOUT_MERGE, 0 /* SOUT to AAL */
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,
MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN,
MT8173_RDMA0_SOUT_COLOR0, 0 /* SOUT to UFOE */
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
MT8173_COLOR0_SEL_IN_OVL0, MT8173_COLOR0_SEL_IN_OVL0
}, {
DDP_COMPONENT_AAL0, DDP_COMPONENT_COLOR0,
MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN,
MT8173_AAL_SEL_IN_MERGE, 0 /* SEL_IN from COLOR0 */
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,
MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN,
MT8173_UFOE_SEL_IN_RDMA0, 0 /* SEL_IN from RDMA0 */
}, {
DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
MT8173_DISP_REG_CONFIG_DSI0_SEL_IN,
MT8173_DSI0_SEL_IN_UFOE, 0, /* SEL_IN from UFOE */
}, {
DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN,
MT8173_OVL1_MOUT_EN_COLOR1, MT8173_OVL1_MOUT_EN_COLOR1
}, {
DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN,
MT8173_GAMMA_MOUT_EN_RDMA1, MT8173_GAMMA_MOUT_EN_RDMA1
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN,
RDMA1_SOUT_MASK, RDMA1_SOUT_DPI0
}, {
DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN,
COLOR1_SEL_IN_OVL1, COLOR1_SEL_IN_OVL1
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8173_DISP_REG_CONFIG_DPI_SEL_IN,
MT8173_DPI0_SEL_IN_MASK, MT8173_DPI0_SEL_IN_RDMA1
}
MMSYS_ROUTE(OVL0, COLOR0,
MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8173_OVL0_MOUT_EN_COLOR0,
MT8173_OVL0_MOUT_EN_COLOR0),
MMSYS_ROUTE(OD0, RDMA0,
MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN, MT8173_OD0_MOUT_EN_RDMA0,
MT8173_OD0_MOUT_EN_RDMA0),
MMSYS_ROUTE(UFOE, DSI0,
MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8173_UFOE_MOUT_EN_DSI0,
MT8173_UFOE_MOUT_EN_DSI0),
MMSYS_ROUTE(COLOR0, AAL0,
MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN, MT8173_COLOR0_SOUT_MERGE,
0 /* SOUT to AAL */),
MMSYS_ROUTE(RDMA0, UFOE,
MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8173_RDMA0_SOUT_COLOR0,
0 /* SOUT to UFOE */),
MMSYS_ROUTE(OVL0, COLOR0,
MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8173_COLOR0_SEL_IN_OVL0,
MT8173_COLOR0_SEL_IN_OVL0),
MMSYS_ROUTE(AAL0, COLOR0,
MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN, MT8173_AAL_SEL_IN_MERGE,
0 /* SEL_IN from COLOR0 */),
MMSYS_ROUTE(RDMA0, UFOE,
MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, MT8173_UFOE_SEL_IN_RDMA0,
0 /* SEL_IN from RDMA0 */),
MMSYS_ROUTE(UFOE, DSI0,
MT8173_DISP_REG_CONFIG_DSI0_SEL_IN, MT8173_DSI0_SEL_IN_UFOE,
0 /* SEL_IN from UFOE */),
MMSYS_ROUTE(OVL1, COLOR1,
MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, MT8173_OVL1_MOUT_EN_COLOR1,
MT8173_OVL1_MOUT_EN_COLOR1),
MMSYS_ROUTE(GAMMA, RDMA1,
MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, MT8173_GAMMA_MOUT_EN_RDMA1,
MT8173_GAMMA_MOUT_EN_RDMA1),
MMSYS_ROUTE(RDMA1, DPI0,
MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
RDMA1_SOUT_DPI0),
MMSYS_ROUTE(OVL1, COLOR1,
MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
COLOR1_SEL_IN_OVL1),
MMSYS_ROUTE(RDMA1, DPI0,
MT8173_DISP_REG_CONFIG_DPI_SEL_IN, MT8173_DPI0_SEL_IN_MASK,
MT8173_DPI0_SEL_IN_RDMA1),
};
#endif /* __SOC_MEDIATEK_MT8173_MMSYS_H */

50
drivers/soc/mediatek/mt8183-mmsys.h
View File

@ -28,35 +28,27 @@
#define MT8183_MMSYS_SW0_RST_B 0x140
static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
MT8183_OVL0_MOUT_EN_OVL0_2L
}, {
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
}, {
DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
MT8183_OVL1_2L_MOUT_EN_RDMA1
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
MT8183_DITHER0_MOUT_IN_DSI0
}, {
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
MT8183_DISP_PATH0_SEL_IN_OVL0_2L
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
MT8183_DPI0_SEL_IN_RDMA1
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
MT8183_RDMA0_SOUT_COLOR0
}
MMSYS_ROUTE(OVL0, OVL_2L0,
MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
MT8183_OVL0_MOUT_EN_OVL0_2L),
MMSYS_ROUTE(OVL_2L0, RDMA0,
MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
MT8183_OVL0_2L_MOUT_EN_DISP_PATH0),
MMSYS_ROUTE(OVL_2L1, RDMA1,
MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
MT8183_OVL1_2L_MOUT_EN_RDMA1),
MMSYS_ROUTE(DITHER0, DSI0,
MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
MT8183_DITHER0_MOUT_IN_DSI0),
MMSYS_ROUTE(OVL_2L0, RDMA0,
MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
MT8183_DISP_PATH0_SEL_IN_OVL0_2L),
MMSYS_ROUTE(RDMA1, DPI0,
MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
MT8183_DPI0_SEL_IN_RDMA1),
MMSYS_ROUTE(RDMA0, COLOR0,
MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
MT8183_RDMA0_SOUT_COLOR0),
};
#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */

88
drivers/soc/mediatek/mt8186-mmsys.h
View File

@ -63,61 +63,39 @@
#define MT8186_MMSYS_SW0_RST_B 0x160
static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
MT8186_OVL0_MOUT_TO_RDMA0
},
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
MT8186_RDMA0_FROM_OVL0
},
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
MT8186_OVL0_GO_BLEND
},
{
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
MT8186_RDMA0_SOUT_TO_COLOR0
},
{
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
MT8186_DITHER0_MOUT_TO_DSI0,
},
{
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
MT8186_DSI0_FROM_DITHER0
},
{
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
MT8186_OVL0_2L_MOUT_TO_RDMA1
},
{
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
MT8186_RDMA1_FROM_OVL0_2L
},
{
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
MT8186_OVL0_2L_GO_BLEND
},
{
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
MT8186_RDMA1_MOUT_TO_DPI0_SEL
},
{
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
MT8186_DPI0_FROM_RDMA1
},
MMSYS_ROUTE(OVL0, RDMA0,
MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
MT8186_OVL0_MOUT_TO_RDMA0),
MMSYS_ROUTE(OVL0, RDMA0,
MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
MT8186_RDMA0_FROM_OVL0),
MMSYS_ROUTE(OVL0, RDMA0,
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
MT8186_OVL0_GO_BLEND),
MMSYS_ROUTE(RDMA0, COLOR0,
MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
MT8186_RDMA0_SOUT_TO_COLOR0),
MMSYS_ROUTE(DITHER0, DSI0,
MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
MT8186_DITHER0_MOUT_TO_DSI0),
MMSYS_ROUTE(DITHER0, DSI0,
MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
MT8186_DSI0_FROM_DITHER0),
MMSYS_ROUTE(OVL_2L0, RDMA1,
MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
MT8186_OVL0_2L_MOUT_TO_RDMA1),
MMSYS_ROUTE(OVL_2L0, RDMA1,
MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
MT8186_RDMA1_FROM_OVL0_2L),
MMSYS_ROUTE(OVL_2L0, RDMA1,
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
MT8186_OVL0_2L_GO_BLEND),
MMSYS_ROUTE(RDMA1, DPI0,
MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
MT8186_RDMA1_MOUT_TO_DPI0_SEL),
MMSYS_ROUTE(RDMA1, DPI0,
MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
MT8186_DPI0_FROM_RDMA1),
};
#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */

266
drivers/soc/mediatek/mt8188-mmsys.h
View File

@ -202,158 +202,126 @@ static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
};
static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0,
MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0,
MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK,
MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_MERGE0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
MT8188_VDO0_DSC_WARP_SEL,
MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK,
MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0,
MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK,
MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
MT8188_VDO0_DISP_RDMA_SEL, MT8188_SOUT_DISP_RDMA0_TO_MASK,
MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8188_VDO0_DISP_DITHER0_SEL_OUT,
MT8188_SOUT_DISP_DITHER0_TO_MASK,
MT8188_SOUT_DISP_DITHER0_TO_DSI0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0,
MT8188_VDO0_DISP_DITHER0_SEL_OUT,
MT8188_SOUT_DISP_DITHER0_TO_MASK,
MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_DP_INTF0
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
},
MMSYS_ROUTE(OVL0, RDMA0,
MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0,
MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0),
MMSYS_ROUTE(OVL0, WDMA0,
MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0,
MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0),
MMSYS_ROUTE(OVL0, RDMA0,
MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK,
MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0),
MMSYS_ROUTE(DITHER0, DSI0,
MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0),
MMSYS_ROUTE(DITHER0, MERGE0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0),
MMSYS_ROUTE(DITHER0, DSC0,
MT8188_VDO0_DSC_WARP_SEL, MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK,
MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0),
MMSYS_ROUTE(DITHER0, DP_INTF0,
MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK,
MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0),
MMSYS_ROUTE(DSC0, MERGE0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT),
MMSYS_ROUTE(MERGE0, DP_INTF0,
MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK,
MT8188_SEL_IN_DP_INTF0_FROM_VPP_MERGE),
MMSYS_ROUTE(DSC0, DSI0,
MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT),
MMSYS_ROUTE(RDMA0, COLOR0,
MT8188_VDO0_DISP_RDMA_SEL, GENMASK(1, 0),
MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0),
MMSYS_ROUTE(DITHER0, DSC0,
MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK,
MT8188_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN),
MMSYS_ROUTE(DITHER0, DSI0,
MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK,
MT8188_SOUT_DISP_DITHER0_TO_DSI0),
MMSYS_ROUTE(DITHER0, MERGE0,
MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK,
MT8188_SOUT_DISP_DITHER0_TO_VPP_MERGE0),
MMSYS_ROUTE(DITHER0, DP_INTF0,
MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK,
MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0),
MMSYS_ROUTE(MERGE0, DP_INTF0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_DP_INTF0),
MMSYS_ROUTE(MERGE0, DPI0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
MMSYS_ROUTE(MERGE0, WDMA0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0),
MMSYS_ROUTE(MERGE0, DSC0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN),
MMSYS_ROUTE(DSC0, DSI0,
MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0),
MMSYS_ROUTE(DSC0, MERGE0,
MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE),
};
static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = {
{
DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
}, {
DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
}, {
DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
}, {
DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8188_SOUT_TO_MIXER_IN1_SEL
}, {
DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8188_SOUT_TO_MIXER_IN2_SEL
}, {
DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8188_SOUT_TO_MIXER_IN3_SEL
}, {
DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8188_SOUT_TO_MIXER_IN4_SEL
}, {
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
}, {
DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
}, {
DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
}, {
DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
}, {
DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
}, {
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
}, {
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
MT8188_MERGE4_SOUT_TO_DPI1_SEL
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL
}
MMSYS_ROUTE(MDP_RDMA0, MERGE1,
MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0),
MMSYS_ROUTE(MDP_RDMA1, MERGE1,
MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1),
MMSYS_ROUTE(MDP_RDMA2, MERGE2,
MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2),
MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8188_SOUT_TO_MIXER_IN1_SEL),
MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8188_SOUT_TO_MIXER_IN2_SEL),
MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8188_SOUT_TO_MIXER_IN3_SEL),
MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8188_SOUT_TO_MIXER_IN4_SEL),
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL),
MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT),
MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT),
MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT),
MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT),
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER),
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT),
MMSYS_ROUTE(MERGE5, DPI1,
MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT),
MMSYS_ROUTE(MERGE5, DPI1,
MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
MT8188_MERGE4_SOUT_TO_DPI1_SEL),
MMSYS_ROUTE(MERGE5, DP_INTF1,
MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT),
MMSYS_ROUTE(MERGE5, DP_INTF1,
MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL),
};
#endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */

71
drivers/soc/mediatek/mt8192-mmsys.h
View File

@ -31,47 +31,36 @@
#define MT8192_DSI0_SEL_IN_DITHER0 0x1
static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
{
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
MT8192_OVL0_MOUT_EN_DISP_RDMA0
}, {
DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
MT8192_OVL2_2L_MOUT_EN_RDMA4
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
MT8192_DITHER0_MOUT_IN_DSI0
}, {
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
MT8192_RDMA0_SEL_IN_OVL0_2L
}, {
DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
MT8192_AAL0_SEL_IN_CCORR0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
MT8192_DSI0_SEL_IN_DITHER0
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
MT8192_RDMA0_SOUT_COLOR0
}, {
DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
MT8192_CCORR0_SOUT_AAL0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
MT8192_DISP_OVL0_GO_BG
}, {
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
MT8192_DISP_OVL0_2L_GO_BLEND
}
MMSYS_ROUTE(OVL_2L0, RDMA0,
MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
MT8192_OVL0_MOUT_EN_DISP_RDMA0),
MMSYS_ROUTE(OVL_2L2, RDMA4,
MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
MT8192_OVL2_2L_MOUT_EN_RDMA4),
MMSYS_ROUTE(DITHER0, DSI0,
MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
MT8192_DITHER0_MOUT_IN_DSI0),
MMSYS_ROUTE(OVL_2L0, RDMA0,
MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
MT8192_RDMA0_SEL_IN_OVL0_2L),
MMSYS_ROUTE(CCORR, AAL0,
MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
MT8192_AAL0_SEL_IN_CCORR0),
MMSYS_ROUTE(DITHER0, DSI0,
MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
MT8192_DSI0_SEL_IN_DITHER0),
MMSYS_ROUTE(RDMA0, COLOR0,
MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
MT8192_RDMA0_SOUT_COLOR0),
MMSYS_ROUTE(CCORR, AAL0,
MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
MT8192_CCORR0_SOUT_AAL0),
MMSYS_ROUTE(OVL0, OVL_2L0,
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
MT8192_DISP_OVL0_GO_BG),
MMSYS_ROUTE(OVL_2L0, RDMA0,
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
MT8192_DISP_OVL0_2L_GO_BLEND),
};
#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */

632
drivers/soc/mediatek/mt8195-mmsys.h
View File

@ -160,370 +160,278 @@
#define MT8195_SVPP3_MDP_RSZ BIT(5)
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
}, {
DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
}, {
DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
}, {
DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
}, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
}, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
}, {
DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
}, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
}, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
}, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
}, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
}, {
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
MT8195_SOUT_DISP_DITHER0_TO_DSI0
}, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
}, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
}, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
}, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
}, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
}, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
}, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_DSI1
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
}, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
}, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
}
MMSYS_ROUTE(OVL0, RDMA0,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0),
MMSYS_ROUTE(OVL0, WDMA0,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0),
MMSYS_ROUTE(OVL0, OVL1,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1),
MMSYS_ROUTE(OVL1, RDMA1,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1),
MMSYS_ROUTE(OVL1, WDMA1,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1),
MMSYS_ROUTE(OVL1, OVL0,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0),
MMSYS_ROUTE(DSC0, MERGE0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT),
MMSYS_ROUTE(DITHER1, MERGE0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1),
MMSYS_ROUTE(MERGE5, MERGE0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0),
MMSYS_ROUTE(DITHER0, DSC0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0),
MMSYS_ROUTE(MERGE0, DSC0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE),
MMSYS_ROUTE(DITHER1, DSC1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1),
MMSYS_ROUTE(MERGE0, DSC1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE),
MMSYS_ROUTE(MERGE0, DP_INTF1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
MMSYS_ROUTE(MERGE0, DPI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
MMSYS_ROUTE(MERGE0, DPI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
MMSYS_ROUTE(DSC1, DP_INTF1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
MMSYS_ROUTE(DSC1, DPI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
MMSYS_ROUTE(DSC1, DPI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
MMSYS_ROUTE(DSC0, DP_INTF1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
MMSYS_ROUTE(DSC0, DPI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
MMSYS_ROUTE(DSC0, DPI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
MMSYS_ROUTE(DSC1, DP_INTF0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT),
MMSYS_ROUTE(MERGE0, DP_INTF0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE),
MMSYS_ROUTE(MERGE5, DP_INTF0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0),
MMSYS_ROUTE(DSC0, DSI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT),
MMSYS_ROUTE(DITHER0, DSI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0),
MMSYS_ROUTE(DSC1, DSI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT),
MMSYS_ROUTE(MERGE0, DSI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
MT8195_SEL_IN_DSI1_FROM_VPP_MERGE),
MMSYS_ROUTE(OVL1, WDMA1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1),
MMSYS_ROUTE(MERGE0, WDMA1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE),
MMSYS_ROUTE(DSC1, DSI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
MMSYS_ROUTE(DSC1, DP_INTF0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
MMSYS_ROUTE(DSC1, DP_INTF1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
MMSYS_ROUTE(DSC1, DPI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
MMSYS_ROUTE(DSC1, DPI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
MMSYS_ROUTE(DSC1, MERGE0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
MMSYS_ROUTE(DITHER1, DSI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
MMSYS_ROUTE(DITHER1, DP_INTF0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
MMSYS_ROUTE(DITHER1, DPI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
MMSYS_ROUTE(DITHER1, DPI1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
MMSYS_ROUTE(OVL0, WDMA0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0),
MMSYS_ROUTE(DITHER0, DSC0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN),
MMSYS_ROUTE(DITHER0, DSI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
MT8195_SOUT_DISP_DITHER0_TO_DSI0),
MMSYS_ROUTE(DITHER1, DSC1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN),
MMSYS_ROUTE(DITHER1, MERGE0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE),
MMSYS_ROUTE(DITHER1, DSI1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
MMSYS_ROUTE(DITHER1, DP_INTF0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
MMSYS_ROUTE(DITHER1, DP_INTF1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
MMSYS_ROUTE(DITHER1, DPI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
MMSYS_ROUTE(DITHER1, DPI1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
MMSYS_ROUTE(MERGE5, MERGE0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE),
MMSYS_ROUTE(MERGE5, DP_INTF0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0),
MMSYS_ROUTE(MERGE0, DSI1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_DSI1),
MMSYS_ROUTE(MERGE0, DP_INTF0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0),
MMSYS_ROUTE(MERGE0, DP_INTF1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
MMSYS_ROUTE(MERGE0, DPI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
MMSYS_ROUTE(MERGE0, DPI1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
MMSYS_ROUTE(MERGE0, WDMA1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1),
MMSYS_ROUTE(MERGE0, DSC0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN),
MMSYS_ROUTE(MERGE0, DSC1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN),
MMSYS_ROUTE(DSC0, DSI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0),
MMSYS_ROUTE(DSC0, DP_INTF1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
MMSYS_ROUTE(DSC0, DPI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
MMSYS_ROUTE(DSC0, DPI1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
MMSYS_ROUTE(DSC0, MERGE0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE),
MMSYS_ROUTE(DSC1, DSI1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1),
MMSYS_ROUTE(DSC1, DP_INTF0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0),
MMSYS_ROUTE(DSC1, DP_INTF1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
MMSYS_ROUTE(DSC1, DPI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
MMSYS_ROUTE(DSC1, DPI1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
MMSYS_ROUTE(DSC1, MERGE0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE),
};
static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = {
{
DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
}, {
DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
}, {
DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
}, {
DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN1_SEL
}, {
DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN2_SEL
}, {
DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN3_SEL
}, {
DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN4_SEL
}, {
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
}, {
DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
}, {
DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
}, {
DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
}, {
DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
}, {
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
}, {
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
MT8195_MERGE4_SOUT_TO_DPI1_SEL
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
}, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
}
MMSYS_ROUTE(MDP_RDMA0, MERGE1,
MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0),
MMSYS_ROUTE(MDP_RDMA1, MERGE1,
MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1),
MMSYS_ROUTE(MDP_RDMA2, MERGE2,
MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2),
MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN1_SEL),
MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN2_SEL),
MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN3_SEL),
MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN4_SEL),
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL),
MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT),
MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT),
MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT),
MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT),
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER),
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT),
MMSYS_ROUTE(MERGE5, DPI1,
MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT),
MMSYS_ROUTE(MERGE5, DPI1,
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
MT8195_MERGE4_SOUT_TO_DPI1_SEL),
MMSYS_ROUTE(MERGE5, DP_INTF1,
MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT),
MMSYS_ROUTE(MERGE5, DP_INTF1,
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL),
};
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */

84
drivers/soc/mediatek/mt8365-mmsys.h
View File

@ -14,8 +14,9 @@
#define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0xfd8
#define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00 0xfdc
#define MT8365_DISP_MS_IN_OUT_MASK GENMASK(3, 0)
#define MT8365_RDMA0_SOUT_COLOR0 0x1
#define MT8365_DITHER_MOUT_EN_DSI0 0x1
#define MT8365_DITHER_MOUT_EN_DSI0 BIT(0)
#define MT8365_DSI0_SEL_IN_DITHER 0x1
#define MT8365_RDMA0_SEL_IN_OVL0 0x0
#define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0
@ -27,56 +28,37 @@
#define MT8365_DPI0_SEL_IN_RDMA1 0x0
static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
MT8365_OVL0_MOUT_PATH0_SEL, MT8365_OVL0_MOUT_PATH0_SEL
},
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
MT8365_RDMA0_SEL_IN_OVL0, MT8365_RDMA0_SEL_IN_OVL0
},
{
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
MT8365_RDMA0_SOUT_COLOR0, MT8365_RDMA0_SOUT_COLOR0
},
{
DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR,
MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
},
{
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
},
{
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
},
{
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
},
{
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK, MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK
},
{
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
MT8365_DPI0_SEL_IN_RDMA1, MT8365_DPI0_SEL_IN_RDMA1
},
{
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
MT8365_RDMA1_SOUT_DPI0, MT8365_RDMA1_SOUT_DPI0
},
MMSYS_ROUTE(OVL0, RDMA0,
MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_OVL0_MOUT_PATH0_SEL),
MMSYS_ROUTE(OVL0, RDMA0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SEL_IN_OVL0),
MMSYS_ROUTE(RDMA0, COLOR0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SOUT_COLOR0),
MMSYS_ROUTE(COLOR0, CCORR,
MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DISP_COLOR_SEL_IN_COLOR0),
MMSYS_ROUTE(DITHER0, DSI0,
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DITHER_MOUT_EN_DSI0),
MMSYS_ROUTE(DITHER0, DSI0,
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DSI0_SEL_IN_DITHER),
MMSYS_ROUTE(RDMA0, COLOR0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0),
MMSYS_ROUTE(RDMA1, DPI0,
MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK,
MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK),
MMSYS_ROUTE(RDMA1, DPI0,
MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DPI0_SEL_IN_RDMA1),
MMSYS_ROUTE(RDMA1, DPI0,
MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA1_SOUT_DPI0),
};
#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */

14
drivers/soc/mediatek/mtk-mmsys.h
View File

@ -80,6 +80,20 @@
#define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit))
/*
* This macro adds a compile time check to make sure that the in/out
* selection bit(s) fit in the register mask, similar to bitfield
* macros, but this does not transform the value.
*/
#define MMSYS_ROUTE(from, to, reg_addr, reg_mask, selection) \
{ DDP_COMPONENT_##from, DDP_COMPONENT_##to, reg_addr, reg_mask, \
(__BUILD_BUG_ON_ZERO_MSG((reg_mask) == 0, "Invalid mask") + \
__BUILD_BUG_ON_ZERO_MSG(~(reg_mask) & (selection), \
#selection " does not fit in " \
#reg_mask) + \
(selection)) \
}
struct mtk_mmsys_routes {
u32 from_comp;
u32 to_comp;

6
drivers/soc/mediatek/mtk-mutex.c
View File

@ -155,6 +155,7 @@
#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23
#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24
#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30
#define MT8188_MUTEX_MOD_DISP1_DPI1 38
#define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39
#define MT8195_MUTEX_MOD_DISP_OVL0 0
@ -289,6 +290,7 @@
#define MT8188_MUTEX_SOF_DSI0 1
#define MT8188_MUTEX_SOF_DP_INTF0 3
#define MT8188_MUTEX_SOF_DP_INTF1 4
#define MT8188_MUTEX_SOF_DPI1 5
#define MT8195_MUTEX_SOF_DSI0 1
#define MT8195_MUTEX_SOF_DSI1 2
#define MT8195_MUTEX_SOF_DP_INTF0 3
@ -301,6 +303,7 @@
#define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7)
#define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7)
#define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7)
#define MT8188_MUTEX_EOF_DPI1 (MT8188_MUTEX_SOF_DPI1 << 7)
#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
@ -472,6 +475,7 @@ static const u8 mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
[DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
[DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
[DDP_COMPONENT_DPI1] = MT8188_MUTEX_MOD_DISP1_DPI1,
[DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
[DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
[DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
@ -686,6 +690,8 @@ static const u16 mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] =
MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
[MUTEX_SOF_DPI1] =
MT8188_MUTEX_SOF_DPI1 | MT8188_MUTEX_EOF_DPI1,
[MUTEX_SOF_DP_INTF0] =
MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
[MUTEX_SOF_DP_INTF1] =

22
drivers/soc/mediatek/mtk-socinfo.c
View File

@ -56,29 +56,39 @@ static struct socinfo_data socinfo_data_table[] = {
MTK_SOCINFO_ENTRY("MT8195", "MT8195GV/EHZA", "Kompanio 1200", 0x81950304, CELL_NOT_USED),
MTK_SOCINFO_ENTRY("MT8195", "MT8195TV/EZA", "Kompanio 1380", 0x81950400, CELL_NOT_USED),
MTK_SOCINFO_ENTRY("MT8195", "MT8195TV/EHZA", "Kompanio 1380", 0x81950404, CELL_NOT_USED),
MTK_SOCINFO_ENTRY("MT8370", "MT8370AV/AZA", "Genio 510", 0x83700000, 0x00000081),
MTK_SOCINFO_ENTRY("MT8390", "MT8390AV/AZA", "Genio 700", 0x83900000, 0x00000080),
MTK_SOCINFO_ENTRY("MT8395", "MT8395AV/ZA", "Genio 1200", 0x83950100, CELL_NOT_USED),
MTK_SOCINFO_ENTRY("MT8395", "MT8395AV/ZA", "Genio 1200", 0x83950800, CELL_NOT_USED),
};
static int mtk_socinfo_create_socinfo_node(struct mtk_socinfo *mtk_socinfop)
{
struct soc_device_attribute *attrs;
static char machine[30] = {0};
struct socinfo_data *data = mtk_socinfop->socinfo_data;
static const char *soc_manufacturer = "MediaTek";
attrs = devm_kzalloc(mtk_socinfop->dev, sizeof(*attrs), GFP_KERNEL);
if (!attrs)
return -ENOMEM;
snprintf(machine, sizeof(machine), "%s (%s)", mtk_socinfop->socinfo_data->marketing_name,
mtk_socinfop->socinfo_data->soc_name);
attrs->family = soc_manufacturer;
attrs->machine = machine;
if (data->marketing_name != NULL && data->marketing_name[0] != '\0')
attrs->family = devm_kasprintf(mtk_socinfop->dev, GFP_KERNEL, "MediaTek %s",
data->marketing_name);
else
attrs->family = soc_manufacturer;
attrs->soc_id = data->soc_name;
/*
* The "machine" field will be populated automatically with the model
* name from board DTS (if available).
**/
mtk_socinfop->soc_dev = soc_device_register(attrs);
if (IS_ERR(mtk_socinfop->soc_dev))
return PTR_ERR(mtk_socinfop->soc_dev);
dev_info(mtk_socinfop->dev, "%s %s SoC detected.\n", soc_manufacturer, attrs->machine);
dev_info(mtk_socinfop->dev, "%s (%s) SoC detected.\n", attrs->family, attrs->soc_id);
return 0;
}