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Merge branch 'add-perout-library-for-rds-ptp-supported-phys'
Divya Koppera says: ==================== Add PEROUT library for RDS PTP supported phys Adds support for PEROUT library, where phy can generate periodic output signal on supported pin out. ==================== Link: https://patch.msgid.link/20250115090634.12941-1-divya.koppera@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
7d2eba0f83
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@ -54,6 +54,243 @@ static int mchp_rds_phy_set_bits_mmd(struct mchp_rds_ptp_clock *clock,
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return phy_set_bits_mmd(phydev, PTP_MMD(clock), addr, val);
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}
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static int mchp_get_pulsewidth(struct phy_device *phydev,
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struct ptp_perout_request *perout_request,
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int *pulse_width)
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{
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struct timespec64 ts_period;
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s64 ts_on_nsec, period_nsec;
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struct timespec64 ts_on;
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static const s64 sup_on_necs[] = {
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100, /* 100ns */
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500, /* 500ns */
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1000, /* 1us */
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5000, /* 5us */
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10000, /* 10us */
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50000, /* 50us */
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100000, /* 100us */
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500000, /* 500us */
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1000000, /* 1ms */
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5000000, /* 5ms */
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10000000, /* 10ms */
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50000000, /* 50ms */
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100000000, /* 100ms */
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200000000, /* 200ms */
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};
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ts_period.tv_sec = perout_request->period.sec;
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ts_period.tv_nsec = perout_request->period.nsec;
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ts_on.tv_sec = perout_request->on.sec;
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ts_on.tv_nsec = perout_request->on.nsec;
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ts_on_nsec = timespec64_to_ns(&ts_on);
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period_nsec = timespec64_to_ns(&ts_period);
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if (period_nsec < 200) {
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phydev_warn(phydev, "perout period small, minimum is 200ns\n");
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return -EOPNOTSUPP;
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}
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for (int i = 0; i < ARRAY_SIZE(sup_on_necs); i++) {
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if (ts_on_nsec <= sup_on_necs[i]) {
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*pulse_width = i;
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break;
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}
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}
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phydev_info(phydev, "pulse width is %d\n", *pulse_width);
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return 0;
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}
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static int mchp_general_event_config(struct mchp_rds_ptp_clock *clock,
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int pulse_width)
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{
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int general_config;
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general_config = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_GEN_CFG,
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MCHP_RDS_PTP_CLOCK);
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if (general_config < 0)
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return general_config;
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general_config &= ~MCHP_RDS_PTP_GEN_CFG_LTC_EVT_MASK;
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general_config |= MCHP_RDS_PTP_GEN_CFG_LTC_EVT_SET(pulse_width);
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general_config &= ~MCHP_RDS_PTP_GEN_CFG_RELOAD_ADD;
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general_config |= MCHP_RDS_PTP_GEN_CFG_POLARITY;
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return mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_GEN_CFG,
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MCHP_RDS_PTP_CLOCK, general_config);
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}
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static int mchp_set_clock_reload(struct mchp_rds_ptp_clock *clock,
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s64 period_sec, u32 period_nsec)
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{
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int rc;
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rc = mchp_rds_phy_write_mmd(clock,
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MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_LO,
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MCHP_RDS_PTP_CLOCK,
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lower_16_bits(period_sec));
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if (rc < 0)
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return rc;
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rc = mchp_rds_phy_write_mmd(clock,
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MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_HI,
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MCHP_RDS_PTP_CLOCK,
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upper_16_bits(period_sec));
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if (rc < 0)
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return rc;
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rc = mchp_rds_phy_write_mmd(clock,
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MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_LO,
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MCHP_RDS_PTP_CLOCK,
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lower_16_bits(period_nsec));
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if (rc < 0)
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return rc;
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return mchp_rds_phy_write_mmd(clock,
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MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_HI,
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MCHP_RDS_PTP_CLOCK,
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upper_16_bits(period_nsec) & 0x3fff);
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}
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static int mchp_set_clock_target(struct mchp_rds_ptp_clock *clock,
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s64 start_sec, u32 start_nsec)
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{
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int rc;
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/* Set the start time */
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rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_SEC_LO,
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MCHP_RDS_PTP_CLOCK,
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lower_16_bits(start_sec));
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if (rc < 0)
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return rc;
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rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_SEC_HI,
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MCHP_RDS_PTP_CLOCK,
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upper_16_bits(start_sec));
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if (rc < 0)
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return rc;
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rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_NS_LO,
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MCHP_RDS_PTP_CLOCK,
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lower_16_bits(start_nsec));
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if (rc < 0)
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return rc;
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return mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_CLK_TRGT_NS_HI,
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MCHP_RDS_PTP_CLOCK,
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upper_16_bits(start_nsec) & 0x3fff);
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}
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static int mchp_rds_ptp_perout_off(struct mchp_rds_ptp_clock *clock)
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{
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u16 general_config;
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int rc;
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/* Set target to too far in the future, effectively disabling it */
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rc = mchp_set_clock_target(clock, 0xFFFFFFFF, 0);
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if (rc < 0)
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return rc;
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general_config = mchp_rds_phy_read_mmd(clock, MCHP_RDS_PTP_GEN_CFG,
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MCHP_RDS_PTP_CLOCK);
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general_config |= MCHP_RDS_PTP_GEN_CFG_RELOAD_ADD;
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rc = mchp_rds_phy_write_mmd(clock, MCHP_RDS_PTP_GEN_CFG,
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MCHP_RDS_PTP_CLOCK, general_config);
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if (rc < 0)
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return rc;
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clock->mchp_rds_ptp_event = -1;
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return 0;
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}
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static bool mchp_get_event(struct mchp_rds_ptp_clock *clock, int pin)
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{
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if (clock->mchp_rds_ptp_event < 0 && pin == clock->event_pin) {
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clock->mchp_rds_ptp_event = pin;
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return true;
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}
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return false;
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}
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static int mchp_rds_ptp_perout(struct ptp_clock_info *ptpci,
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struct ptp_perout_request *perout, int on)
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{
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struct mchp_rds_ptp_clock *clock = container_of(ptpci,
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struct mchp_rds_ptp_clock,
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caps);
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struct phy_device *phydev = clock->phydev;
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int ret, event_pin, pulsewidth;
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/* Reject requests with unsupported flags */
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if (perout->flags & ~PTP_PEROUT_DUTY_CYCLE)
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return -EOPNOTSUPP;
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event_pin = ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
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perout->index);
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if (event_pin != clock->event_pin)
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return -EINVAL;
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if (!on) {
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ret = mchp_rds_ptp_perout_off(clock);
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return ret;
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}
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if (!mchp_get_event(clock, event_pin))
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return -EINVAL;
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ret = mchp_get_pulsewidth(phydev, perout, &pulsewidth);
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if (ret < 0)
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return ret;
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/* Configure to pulse every period */
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ret = mchp_general_event_config(clock, pulsewidth);
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if (ret < 0)
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return ret;
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ret = mchp_set_clock_target(clock, perout->start.sec,
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perout->start.nsec);
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if (ret < 0)
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return ret;
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return mchp_set_clock_reload(clock, perout->period.sec,
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perout->period.nsec);
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}
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static int mchp_rds_ptpci_enable(struct ptp_clock_info *ptpci,
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struct ptp_clock_request *request, int on)
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{
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switch (request->type) {
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case PTP_CLK_REQ_PEROUT:
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return mchp_rds_ptp_perout(ptpci, &request->perout, on);
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default:
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return -EINVAL;
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}
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}
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static int mchp_rds_ptpci_verify(struct ptp_clock_info *ptpci, unsigned int pin,
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enum ptp_pin_function func, unsigned int chan)
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{
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struct mchp_rds_ptp_clock *clock = container_of(ptpci,
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struct mchp_rds_ptp_clock,
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caps);
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if (!(pin == clock->event_pin && chan == 0))
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return -1;
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switch (func) {
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case PTP_PF_NONE:
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case PTP_PF_PEROUT:
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break;
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default:
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return -1;
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}
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return 0;
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}
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static int mchp_rds_ptp_flush_fifo(struct mchp_rds_ptp_clock *clock,
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enum mchp_rds_ptp_fifo_dir dir)
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{
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@ -479,6 +716,16 @@ static int mchp_rds_ptp_ltc_adjtime(struct ptp_clock_info *info, s64 delta)
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MCHP_RDS_PTP_CMD_CTL_LTC_STEP_NSEC);
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}
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mutex_unlock(&clock->ptp_lock);
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info->gettime64(info, &ts);
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mutex_lock(&clock->ptp_lock);
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/* Target update is required for pulse generation on events that
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* are enabled
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*/
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if (clock->mchp_rds_ptp_event >= 0)
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mchp_set_clock_target(clock,
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ts.tv_sec + MCHP_RDS_PTP_BUFFER_TIME, 0);
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out_unlock:
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mutex_unlock(&clock->ptp_lock);
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@ -989,16 +1236,37 @@ struct mchp_rds_ptp_clock *mchp_rds_ptp_probe(struct phy_device *phydev, u8 mmd,
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clock->mmd = mmd;
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mutex_init(&clock->ptp_lock);
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clock->pin_config = devm_kmalloc_array(&phydev->mdio.dev,
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MCHP_RDS_PTP_N_PIN,
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sizeof(*clock->pin_config),
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GFP_KERNEL);
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if (!clock->pin_config)
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return ERR_PTR(-ENOMEM);
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for (int i = 0; i < MCHP_RDS_PTP_N_PIN; ++i) {
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struct ptp_pin_desc *p = &clock->pin_config[i];
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memset(p, 0, sizeof(*p));
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snprintf(p->name, sizeof(p->name), "pin%d", i);
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p->index = i;
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p->func = PTP_PF_NONE;
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}
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/* Register PTP clock */
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clock->caps.owner = THIS_MODULE;
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snprintf(clock->caps.name, 30, "%s", phydev->drv->name);
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clock->caps.max_adj = MCHP_RDS_PTP_MAX_ADJ;
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clock->caps.n_ext_ts = 0;
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clock->caps.pps = 0;
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clock->caps.n_pins = MCHP_RDS_PTP_N_PIN;
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clock->caps.n_per_out = MCHP_RDS_PTP_N_PEROUT;
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clock->caps.pin_config = clock->pin_config;
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clock->caps.adjfine = mchp_rds_ptp_ltc_adjfine;
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clock->caps.adjtime = mchp_rds_ptp_ltc_adjtime;
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clock->caps.gettime64 = mchp_rds_ptp_ltc_gettime64;
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clock->caps.settime64 = mchp_rds_ptp_ltc_settime64;
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clock->caps.enable = mchp_rds_ptpci_enable;
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clock->caps.verify = mchp_rds_ptpci_verify;
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clock->caps.getcrosststamp = NULL;
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clock->ptp_clock = ptp_clock_register(&clock->caps,
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&phydev->mdio.dev);
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if (IS_ERR(clock->ptp_clock))
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@ -1021,6 +1289,8 @@ struct mchp_rds_ptp_clock *mchp_rds_ptp_probe(struct phy_device *phydev, u8 mmd,
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phydev->mii_ts = &clock->mii_ts;
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clock->mchp_rds_ptp_event = -1;
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/* Timestamp selected by default to keep legacy API */
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phydev->default_timestamp = true;
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@ -130,6 +130,23 @@
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#define MCHP_RDS_PTP_TSU_HARD_RESET 0xc1
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#define MCHP_RDS_PTP_TSU_HARDRESET BIT(0)
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#define MCHP_RDS_PTP_CLK_TRGT_SEC_HI 0x15
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#define MCHP_RDS_PTP_CLK_TRGT_SEC_LO 0x16
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#define MCHP_RDS_PTP_CLK_TRGT_NS_HI 0x17
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#define MCHP_RDS_PTP_CLK_TRGT_NS_LO 0x18
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#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_HI 0x19
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#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_LO 0x1a
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#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_HI 0x1b
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#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_LO 0x1c
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#define MCHP_RDS_PTP_GEN_CFG 0x01
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#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_MASK GENMASK(11, 8)
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#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_SET(value) (((value) & 0xF) << 4)
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#define MCHP_RDS_PTP_GEN_CFG_RELOAD_ADD BIT(0)
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#define MCHP_RDS_PTP_GEN_CFG_POLARITY BIT(1)
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/* Represents 1ppm adjustment in 2^32 format with
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* each nsec contains 4 clock cycles in 250MHz.
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* The value is calculated as following: (1/1000000)/((2^-32)/4)
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@ -138,6 +155,10 @@
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#define MCHP_RDS_PTP_FIFO_SIZE 8
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#define MCHP_RDS_PTP_MAX_ADJ 31249999
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#define MCHP_RDS_PTP_BUFFER_TIME 2
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#define MCHP_RDS_PTP_N_PIN 4
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#define MCHP_RDS_PTP_N_PEROUT 1
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#define BASE_CLK(p) ((p)->clk_base_addr)
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#define BASE_PORT(p) ((p)->port_base_addr)
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#define PTP_MMD(p) ((p)->mmd)
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@ -176,6 +197,9 @@ struct mchp_rds_ptp_clock {
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/* Lock for phc */
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struct mutex ptp_lock;
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u8 mmd;
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int mchp_rds_ptp_event;
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int event_pin;
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struct ptp_pin_desc *pin_config;
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};
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struct mchp_rds_ptp_rx_ts {
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@ -238,6 +238,9 @@
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#define LAN887X_INT_MSK_LINK_UP_MSK BIT(1)
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#define LAN887X_INT_MSK_LINK_DOWN_MSK BIT(0)
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#define LAN887X_MX_CHIP_TOP_REG_CONTROL1 0xF002
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#define LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN BIT(8)
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#define LAN887X_MX_CHIP_TOP_LINK_MSK (LAN887X_INT_MSK_LINK_UP_MSK |\
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LAN887X_INT_MSK_LINK_DOWN_MSK)
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@ -1286,6 +1289,15 @@ static int lan887x_phy_init(struct phy_device *phydev)
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if (IS_ERR(priv->clock))
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return PTR_ERR(priv->clock);
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/* Enable pin mux for EVT */
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phy_modify_mmd(phydev, MDIO_MMD_VEND1,
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LAN887X_MX_CHIP_TOP_REG_CONTROL1,
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LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN,
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LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN);
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/* Initialize pin numbers specific to PEROUT */
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priv->clock->event_pin = 3;
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priv->init_done = true;
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}
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@ -2154,7 +2166,7 @@ static struct phy_driver microchip_t1_phy_driver[] = {
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module_phy_driver(microchip_t1_phy_driver);
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static const struct mdio_device_id __maybe_unused microchip_t1_tbl[] = {
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static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = {
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{ PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_LAN937X) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_LAN887X) },
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