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media: staging: media: imx6-mipi-csi2: replace spaces with tabs for alignment
Replace spaces with tabs to align register value definitions, making it easier to add new entries and maintain consistent formatting. Also use a space between the type and field in struct csi2_dev. No functional change. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patch.msgid.link/20260116-stage-csi2-cleanup-v2-1-a56e9cb25196@nxp.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
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@ -23,65 +23,65 @@
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* there must be 5 pads: 1 input pad from sensor, and
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* the 4 virtual channel output pads
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*/
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#define CSI2_SINK_PAD 0
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#define CSI2_NUM_SINK_PADS 1
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#define CSI2_NUM_SRC_PADS 4
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#define CSI2_NUM_PADS 5
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#define CSI2_SINK_PAD 0
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#define CSI2_NUM_SINK_PADS 1
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#define CSI2_NUM_SRC_PADS 4
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#define CSI2_NUM_PADS 5
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/*
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* The default maximum bit-rate per lane in Mbps, if the
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* source subdev does not provide V4L2_CID_LINK_FREQ.
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*/
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#define CSI2_DEFAULT_MAX_MBPS 849
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#define CSI2_DEFAULT_MAX_MBPS 849
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struct csi2_dev {
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struct device *dev;
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struct v4l2_subdev sd;
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struct device *dev;
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struct v4l2_subdev sd;
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struct v4l2_async_notifier notifier;
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struct media_pad pad[CSI2_NUM_PADS];
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struct clk *dphy_clk;
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struct clk *pllref_clk;
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struct clk *pix_clk; /* what is this? */
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void __iomem *base;
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struct media_pad pad[CSI2_NUM_PADS];
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struct clk *dphy_clk;
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struct clk *pllref_clk;
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struct clk *pix_clk; /* what is this? */
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void __iomem *base;
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struct v4l2_subdev *remote;
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unsigned int remote_pad;
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unsigned short data_lanes;
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struct v4l2_subdev *remote;
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unsigned int remote_pad;
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unsigned short data_lanes;
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/* lock to protect all members below */
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struct mutex lock;
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struct v4l2_mbus_framefmt format_mbus;
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int stream_count;
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struct v4l2_subdev *src_sd;
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bool sink_linked[CSI2_NUM_SRC_PADS];
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int stream_count;
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struct v4l2_subdev *src_sd;
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bool sink_linked[CSI2_NUM_SRC_PADS];
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};
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#define DEVICE_NAME "imx6-mipi-csi2"
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/* Register offsets */
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#define CSI2_VERSION 0x000
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#define CSI2_N_LANES 0x004
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#define CSI2_PHY_SHUTDOWNZ 0x008
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#define CSI2_DPHY_RSTZ 0x00c
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#define CSI2_RESETN 0x010
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#define CSI2_PHY_STATE 0x014
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#define PHY_STOPSTATEDATA_BIT 4
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#define PHY_STOPSTATEDATA(n) BIT(PHY_STOPSTATEDATA_BIT + (n))
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#define PHY_RXCLKACTIVEHS BIT(8)
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#define PHY_RXULPSCLKNOT BIT(9)
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#define PHY_STOPSTATECLK BIT(10)
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#define CSI2_DATA_IDS_1 0x018
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#define CSI2_DATA_IDS_2 0x01c
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#define CSI2_ERR1 0x020
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#define CSI2_ERR2 0x024
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#define CSI2_MSK1 0x028
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#define CSI2_MSK2 0x02c
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#define CSI2_PHY_TST_CTRL0 0x030
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#define CSI2_VERSION 0x000
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#define CSI2_N_LANES 0x004
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#define CSI2_PHY_SHUTDOWNZ 0x008
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#define CSI2_DPHY_RSTZ 0x00c
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#define CSI2_RESETN 0x010
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#define CSI2_PHY_STATE 0x014
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#define PHY_STOPSTATEDATA_BIT 4
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#define PHY_STOPSTATEDATA(n) BIT(PHY_STOPSTATEDATA_BIT + (n))
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#define PHY_RXCLKACTIVEHS BIT(8)
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#define PHY_RXULPSCLKNOT BIT(9)
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#define PHY_STOPSTATECLK BIT(10)
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#define CSI2_DATA_IDS_1 0x018
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#define CSI2_DATA_IDS_2 0x01c
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#define CSI2_ERR1 0x020
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#define CSI2_ERR2 0x024
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#define CSI2_MSK1 0x028
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#define CSI2_MSK2 0x02c
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#define CSI2_PHY_TST_CTRL0 0x030
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#define PHY_TESTCLR BIT(0)
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#define PHY_TESTCLK BIT(1)
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#define CSI2_PHY_TST_CTRL1 0x034
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#define CSI2_PHY_TST_CTRL1 0x034
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#define PHY_TESTEN BIT(16)
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/*
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* i.MX CSI2IPU Gasket registers follow. The CSI2IPU gasket is
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@ -106,13 +106,13 @@ static inline struct csi2_dev *notifier_to_dev(struct v4l2_async_notifier *n)
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* reference manual is as follows:
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*
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* 1. Deassert presetn signal (global reset).
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* It's not clear what this "global reset" signal is (maybe APB
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* global reset), but in any case this step would be probably
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* be carried out during driver load in csi2_probe().
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* It's not clear what this "global reset" signal is (maybe APB
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* global reset), but in any case this step would be probably
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* be carried out during driver load in csi2_probe().
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*
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* 2. Configure MIPI Camera Sensor to put all Tx lanes in LP-11 state.
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* This must be carried out by the MIPI sensor's s_power(ON) subdev
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* op.
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* This must be carried out by the MIPI sensor's s_power(ON) subdev
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* op.
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*
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* 3. D-PHY initialization.
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* 4. CSI2 Controller programming (Set N_LANES, deassert PHY_SHUTDOWNZ,
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