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drm: renesas: rzg2l_mipi_dsi: Increase reset deassertion delay

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The RZ/G2L hardware manual (Rev. 1.50, May 2025), Section 34.4.2.1,
requires waiting at least 1 msec after deasserting the CMN_RSTB signal
before the DSI-Tx module is ready. Increase the delay from 1 usec to
1 msec by replacing udelay(1) with fsleep(1000) for RZ/G2L SoCs.

Fixes: 7a043f978e ("drm: rcar-du: Add RZ/G2L DSI driver")
Cc: stable@vger.kernel.org
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/20260330104450.128512-3-biju.das.jz@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
This commit is contained in:
Biju Das 2026-03-30 11:44:45 +01:00
parent 5bfa858d53
commit 7cbba8a8ba
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
View File

@ -528,7 +528,7 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
if (ret < 0)
return ret;
udelay(1);
fsleep(1000);
return 0;
}