arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3

Add ADC0 and ADC1 for S32G2 and S32G3 SoCs.

Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
Reviewed-by: Enric Balletbo i Serra <eballetb@redhat.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Khristine Andreea Barbulescu 2026-05-14 10:26:39 +02:00 committed by Frank Li
parent 65c16cd0de
commit 7ca25f0fa0
2 changed files with 40 additions and 0 deletions

View File

@ -563,6 +563,16 @@ i2c2: i2c@401ec000 {
status = "disabled";
};
adc0: adc@401f8000 {
compatible = "nxp,s32g2-sar-adc";
reg = <0x401f8000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 0x41>;
dmas = <&edma0 0 32>;
dma-names = "rx";
status = "disabled";
};
swt4: watchdog@40200000 {
compatible = "nxp,s32g2-swt";
reg = <0x40200000 0x1000>;
@ -735,6 +745,16 @@ i2c4: i2c@402dc000 {
status = "disabled";
};
adc1: adc@402e8000 {
compatible = "nxp,s32g2-sar-adc";
reg = <0x402e8000 0x1000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 0x41>;
dmas = <&edma1 1 32>;
dma-names = "rx";
status = "disabled";
};
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g2-usdhc";
reg = <0x402f0000 0x1000>;

View File

@ -626,6 +626,16 @@ i2c2: i2c@401ec000 {
status = "disabled";
};
adc0: adc@401f8000 {
compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc";
reg = <0x401f8000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 0x41>;
dmas = <&edma0 0 32>;
dma-names = "rx";
status = "disabled";
};
swt4: watchdog@40200000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40200000 0x1000>;
@ -810,6 +820,16 @@ i2c4: i2c@402dc000 {
status = "disabled";
};
adc1: adc@402e8000 {
compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc";
reg = <0x402e8000 0x1000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 0x41>;
dmas = <&edma1 1 32>;
dma-names = "rx";
status = "disabled";
};
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g3-usdhc",
"nxp,s32g2-usdhc";