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drm/amd/display: Clean up warnings in amdgpu_dm_pp_smu.c
Fixes the following category of checkpatch warning: WARNING: Block comments use a trailing */ on a separate line + * non-boosted one. */ WARNING: suspect code indent for conditional statements (8, 24) + if ((adev->asic_type >= CHIP_POLARIS10) && [...] + return true; Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -334,7 +334,8 @@ bool dm_pp_get_clock_levels_by_type(
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if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
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/* This clock is higher the validation clock.
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* Than means the previous one is the highest
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* non-boosted one. */
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* non-boosted one.
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*/
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DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
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dc_clks->num_levels, i);
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dc_clks->num_levels = i > 0 ? i : 1;
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@ -406,10 +407,10 @@ bool dm_pp_notify_wm_clock_changes(
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* TODO: expand this to other ASICs
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*/
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if ((adev->asic_type >= CHIP_POLARIS10) &&
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(adev->asic_type <= CHIP_VEGAM) &&
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!amdgpu_dpm_set_watermarks_for_clocks_ranges(adev,
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(void *)wm_with_clock_ranges))
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return true;
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(adev->asic_type <= CHIP_VEGAM) &&
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!amdgpu_dpm_set_watermarks_for_clocks_ranges(adev,
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(void *)wm_with_clock_ranges))
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return true;
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return false;
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}
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