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drm/amd/display: Add DMUB support for dcn42
DMUB support for DCN 4.2 Signed-off-by: Roman Li <Roman.Li@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Roman Li
Alex Deucher
parent
bd096a56da
commit
7c4757c20e
752
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
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752
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
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@ -0,0 +1,752 @@
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// SPDX-License-Identifier: MIT
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//
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// Copyright 2026 Advanced Micro Devices, Inc.
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#include "../dmub_srv.h"
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#include "dmub_reg.h"
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#include "dmub_dcn35.h"
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#include "dmub_dcn401.h"
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#include "dmub_dcn42.h"
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#include "dcn/dcn_4_2_0_offset.h"
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#include "dcn/dcn_4_2_0_sh_mask.h"
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#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
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#define CTX dmub
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#define REGS dmub->regs_dcn42
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#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
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void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)
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{
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struct dmub_srv_dcn42_regs *regs = dmub->regs_dcn42;
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#define REG_STRUCT regs
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#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
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DMUB_DCN42_REGS()
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DMCUB_INTERNAL_REGS()
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#undef DMUB_SR
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#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
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DMUB_DCN42_FIELDS()
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#undef DMUB_SF
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#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
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DMUB_DCN42_FIELDS()
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#undef DMUB_SF
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#undef REG_STRUCT
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}
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void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
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{
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union dmub_fw_boot_options boot_options = {0};
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union dmub_fw_boot_options cur_boot_options = {0};
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cur_boot_options = dmub_dcn42_get_fw_boot_option(dmub);
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boot_options.bits.z10_disable = params->disable_z10;
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boot_options.bits.dpia_supported = params->dpia_supported;
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boot_options.bits.enable_dpia = cur_boot_options.bits.enable_dpia && !params->disable_dpia;
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boot_options.bits.usb4_cm_version = params->usb4_cm_version;
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boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported;
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boot_options.bits.power_optimization = params->power_optimization;
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boot_options.bits.disable_clk_ds = params->disallow_dispclk_dppclk_ds;
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boot_options.bits.disable_clk_gate = params->disable_clock_gate;
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boot_options.bits.ips_disable = params->disable_ips;
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boot_options.bits.ips_sequential_ono = params->ips_sequential_ono;
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boot_options.bits.disable_sldo_opt = params->disable_sldo_opt;
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boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig;
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boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc;
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boot_options.bits.skip_phy_access = params->disallow_phy_access;
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boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation;
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REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
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}
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static void dmub_dcn42_get_fb_base_offset(struct dmub_srv *dmub,
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uint64_t *fb_base,
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uint64_t *fb_offset)
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{
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uint32_t tmp;
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/*
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if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) {
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*fb_base = dmub->soc_fb_info.fb_base;
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*fb_offset = dmub->soc_fb_info.fb_offset;
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return;
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}
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*/
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REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
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*fb_base = (uint64_t)tmp << 24;
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REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
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*fb_offset = (uint64_t)tmp << 24;
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}
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static inline void dmub_dcn42_translate_addr(const union dmub_addr *addr_in,
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uint64_t fb_base,
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uint64_t fb_offset,
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union dmub_addr *addr_out)
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{
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addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
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}
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void dmub_dcn42_reset(struct dmub_srv *dmub)
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{
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union dmub_gpint_data_register cmd;
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const uint32_t timeout = 100000;
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uint32_t in_reset, is_enabled, scratch, i, pwait_mode;
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REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
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REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled);
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if (in_reset == 0 && is_enabled != 0) {
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cmd.bits.status = 1;
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cmd.bits.command_code = DMUB_GPINT__STOP_FW;
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cmd.bits.param = 0;
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dmub->hw_funcs.set_gpint(dmub, cmd);
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for (i = 0; i < timeout; ++i) {
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if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
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break;
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udelay(1);
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}
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for (i = 0; i < timeout; ++i) {
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scratch = REG_READ(DMCUB_SCRATCH7);
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if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
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break;
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udelay(1);
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}
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for (i = 0; i < timeout; ++i) {
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REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode);
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if (pwait_mode & (1 << 0))
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break;
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udelay(1);
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}
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/* Force reset in case we timed out, DMCUB is likely hung. */
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}
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if (is_enabled) {
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REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
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udelay(1);
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REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
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}
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REG_WRITE(DMCUB_INBOX1_RPTR, 0);
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REG_WRITE(DMCUB_INBOX1_WPTR, 0);
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REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
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REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
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REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
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REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
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REG_WRITE(DMCUB_SCRATCH0, 0);
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/* Clear the GPINT command manually so we don't send anything during boot. */
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cmd.all = 0;
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dmub->hw_funcs.set_gpint(dmub, cmd);
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}
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void dmub_dcn42_reset_release(struct dmub_srv *dmub)
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{
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REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
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REG_UPDATE_3(DMU_CLK_CNTL,
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LONO_DISPCLK_GATE_DISABLE, 1,
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LONO_SOCCLK_GATE_DISABLE, 1,
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LONO_DMCUBCLK_GATE_DISABLE, 1);
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REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
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REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
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REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
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}
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void dmub_dcn42_backdoor_load(struct dmub_srv *dmub,
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const struct dmub_window *cw0,
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const struct dmub_window *cw1)
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{
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union dmub_addr offset;
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uint64_t fb_base, fb_offset;
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dmub_dcn42_get_fb_base_offset(dmub, &fb_base, &fb_offset);
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dmub_dcn42_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
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REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
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REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
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DMCUB_REGION3_CW0_ENABLE, 1);
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dmub_dcn42_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
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REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
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REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
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DMCUB_REGION3_CW1_ENABLE, 1);
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/* TODO: Do we need to set DMCUB_MEM_UNIT_ID? */
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REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0);
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}
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void dmub_dcn42_backdoor_load_zfb_mode(struct dmub_srv *dmub,
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const struct dmub_window *cw0,
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const struct dmub_window *cw1)
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{
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union dmub_addr offset;
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REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
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offset = cw0->offset;
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REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
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REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
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DMCUB_REGION3_CW0_ENABLE, 1);
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offset = cw1->offset;
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REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
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REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
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DMCUB_REGION3_CW1_ENABLE, 1);
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REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
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0x20);
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}
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void dmub_dcn42_setup_windows(struct dmub_srv *dmub,
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const struct dmub_window *cw2,
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const struct dmub_window *cw3,
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const struct dmub_window *cw4,
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const struct dmub_window *cw5,
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const struct dmub_window *cw6,
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const struct dmub_window *region6)
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{
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union dmub_addr offset;
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offset = cw3->offset;
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REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
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REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
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DMCUB_REGION3_CW3_ENABLE, 1);
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offset = cw4->offset;
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REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
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REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
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DMCUB_REGION3_CW4_ENABLE, 1);
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offset = cw5->offset;
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REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
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REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
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DMCUB_REGION3_CW5_ENABLE, 1);
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REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
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REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
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DMCUB_REGION5_TOP_ADDRESS,
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cw5->region.top - cw5->region.base - 1,
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DMCUB_REGION5_ENABLE, 1);
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offset = cw6->offset;
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REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
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REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
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DMCUB_REGION3_CW6_ENABLE, 1);
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offset = region6->offset;
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REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part);
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REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0,
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DMCUB_REGION6_TOP_ADDRESS,
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region6->region.top - region6->region.base - 1,
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DMCUB_REGION6_ENABLE, 1);
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}
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uint32_t dmub_dcn42_get_inbox1_wptr(struct dmub_srv *dmub)
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{
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return REG_READ(DMCUB_INBOX1_WPTR);
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}
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uint32_t dmub_dcn42_get_inbox1_rptr(struct dmub_srv *dmub)
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{
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return REG_READ(DMCUB_INBOX1_RPTR);
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}
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void dmub_dcn42_setup_out_mailbox(struct dmub_srv *dmub,
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const struct dmub_region *outbox1)
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{
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REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
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REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
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}
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uint32_t dmub_dcn42_get_outbox1_wptr(struct dmub_srv *dmub)
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{
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/**
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* outbox1 wptr register is accessed without locks (dal & dc)
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* and to be called only by dmub_srv_stat_get_notification()
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*/
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return REG_READ(DMCUB_OUTBOX1_WPTR);
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}
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void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
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{
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/**
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* outbox1 rptr register is accessed without locks (dal & dc)
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* and to be called only by dmub_srv_stat_get_notification()
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*/
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REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
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}
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bool dmub_dcn42_is_supported(struct dmub_srv *dmub)
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{
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uint32_t supported = 0;
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REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
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return supported;
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}
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union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub)
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{
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union dmub_fw_boot_options option;
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option.all = REG_READ(DMCUB_SCRATCH14);
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return option;
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}
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void dmub_dcn42_setup_outbox0(struct dmub_srv *dmub,
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const struct dmub_region *outbox0)
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{
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REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
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REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
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}
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bool dmub_dcn42_should_detect(struct dmub_srv *dmub)
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{
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uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0);
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bool should_detect = (fw_boot_status & DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED) != 0;
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return should_detect;
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}
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void dmub_dcn42_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)
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{
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REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
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}
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uint32_t dmub_dcn42_read_inbox0_ack_register(struct dmub_srv *dmub)
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{
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return REG_READ(DMCUB_SCRATCH17);
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}
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bool dmub_dcn42_is_hw_powered_up(struct dmub_srv *dmub)
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{
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union dmub_fw_boot_status status;
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uint32_t is_enable;
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REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable);
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if (is_enable == 0)
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return false;
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status.all = REG_READ(DMCUB_SCRATCH0);
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return (status.bits.dal_fw && status.bits.hw_power_init_done && status.bits.mailbox_rdy) ||
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(!status.bits.dal_fw && status.bits.mailbox_rdy);
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}
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|
||||
void dmub_dcn42_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
|
||||
{
|
||||
REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
|
||||
}
|
||||
|
||||
bool dmub_dcn42_is_hw_init(struct dmub_srv *dmub)
|
||||
{
|
||||
union dmub_fw_boot_status status;
|
||||
uint32_t is_hw_init;
|
||||
|
||||
status.all = REG_READ(DMCUB_SCRATCH0);
|
||||
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
|
||||
|
||||
return is_hw_init != 0 && status.bits.dal_fw;
|
||||
}
|
||||
|
||||
union dmub_fw_boot_status dmub_dcn42_get_fw_boot_status(struct dmub_srv *dmub)
|
||||
{
|
||||
union dmub_fw_boot_status status;
|
||||
|
||||
status.all = REG_READ(DMCUB_SCRATCH0);
|
||||
return status;
|
||||
}
|
||||
|
||||
void dmub_dcn42_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
|
||||
{
|
||||
union dmub_fw_boot_options boot_options;
|
||||
boot_options.all = REG_READ(DMCUB_SCRATCH14);
|
||||
boot_options.bits.skip_phy_init_panel_sequence = skip;
|
||||
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
|
||||
}
|
||||
|
||||
void dmub_dcn42_configure_dmub_in_system_memory(struct dmub_srv *dmub)
|
||||
{
|
||||
/* DMCUB_REGION3_TMR_AXI_SPACE values:
|
||||
* 0b011 (0x3) - FB physical address
|
||||
* 0b100 (0x4) - GPU virtual address
|
||||
*
|
||||
* Default value is 0x3 (FB Physical address for TMR). When programming
|
||||
* DMUB to be in system memory, change to 0x4. The system memory allocated
|
||||
* is accessible by both GPU and CPU, so we use GPU virtual address.
|
||||
*/
|
||||
REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
|
||||
}
|
||||
|
||||
void dmub_dcn42_clear_inbox0_ack_register(struct dmub_srv *dmub)
|
||||
{
|
||||
REG_WRITE(DMCUB_SCRATCH17, 0);
|
||||
}
|
||||
|
||||
void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,
|
||||
union dmub_rb_cmd *cmd)
|
||||
{
|
||||
uint32_t *dwords = (uint32_t *)cmd;
|
||||
int32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes;
|
||||
uint32_t msg_index;
|
||||
static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch");
|
||||
|
||||
/* read remaining data based on payload size */
|
||||
for (msg_index = 0; msg_index < 15; msg_index++) {
|
||||
if (payload_size_bytes <= msg_index * 4) {
|
||||
break;
|
||||
}
|
||||
|
||||
switch (msg_index) {
|
||||
case 0:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[msg_index + 1]);
|
||||
break;
|
||||
case 1:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[msg_index + 1]);
|
||||
break;
|
||||
case 2:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[msg_index + 1]);
|
||||
break;
|
||||
case 3:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[msg_index + 1]);
|
||||
break;
|
||||
case 4:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[msg_index + 1]);
|
||||
break;
|
||||
case 5:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[msg_index + 1]);
|
||||
break;
|
||||
case 6:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[msg_index + 1]);
|
||||
break;
|
||||
case 7:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[msg_index + 1]);
|
||||
break;
|
||||
case 8:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[msg_index + 1]);
|
||||
break;
|
||||
case 9:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[msg_index + 1]);
|
||||
break;
|
||||
case 10:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[msg_index + 1]);
|
||||
break;
|
||||
case 11:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[msg_index + 1]);
|
||||
break;
|
||||
case 12:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[msg_index + 1]);
|
||||
break;
|
||||
case 13:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[msg_index + 1]);
|
||||
break;
|
||||
case 14:
|
||||
REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[msg_index + 1]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* writing to INBOX RDY register will trigger DMUB REG INBOX0 RDY
|
||||
* interrupt.
|
||||
*/
|
||||
REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[0]);
|
||||
}
|
||||
|
||||
uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub)
|
||||
{
|
||||
uint32_t status;
|
||||
|
||||
REG_GET(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT, &status);
|
||||
return status;
|
||||
}
|
||||
|
||||
void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,
|
||||
union dmub_rb_cmd *cmd)
|
||||
{
|
||||
uint32_t *dwords = (uint32_t *)cmd;
|
||||
|
||||
static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch");
|
||||
|
||||
dwords[0] = REG_READ(DMCUB_REG_INBOX0_RSP);
|
||||
dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG0);
|
||||
dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG1);
|
||||
dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG2);
|
||||
dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG3);
|
||||
dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG4);
|
||||
dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG5);
|
||||
dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG6);
|
||||
dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG7);
|
||||
dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG8);
|
||||
dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG9);
|
||||
dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG10);
|
||||
dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG11);
|
||||
dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG12);
|
||||
dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG13);
|
||||
dwords[15] = REG_READ(DMCUB_REG_INBOX0_MSG14);
|
||||
}
|
||||
|
||||
void dmub_dcn42_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)
|
||||
{
|
||||
REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 1);
|
||||
}
|
||||
|
||||
void dmub_dcn42_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)
|
||||
{
|
||||
REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 0);
|
||||
}
|
||||
|
||||
void dmub_dcn42_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable)
|
||||
{
|
||||
REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN, enable ? 1:0);
|
||||
}
|
||||
|
||||
void dmub_dcn42_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub)
|
||||
{
|
||||
REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 1);
|
||||
REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 0);
|
||||
}
|
||||
|
||||
void dmub_dcn42_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg)
|
||||
{
|
||||
*msg = REG_READ(DMCUB_REG_OUTBOX0_MSG0);
|
||||
}
|
||||
|
||||
|
||||
void dmub_dcn42_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable)
|
||||
{
|
||||
REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN, enable ? 1:0);
|
||||
}
|
||||
|
||||
uint32_t dmub_dcn42_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub)
|
||||
{
|
||||
uint32_t status;
|
||||
|
||||
REG_GET(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT, &status);
|
||||
return status;
|
||||
}
|
||||
|
||||
void dmub_dcn42_setup_mailbox(struct dmub_srv *dmub,
|
||||
const struct dmub_region *inbox1)
|
||||
{
|
||||
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
|
||||
REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
|
||||
}
|
||||
|
||||
void dmub_dcn42_set_gpint(struct dmub_srv *dmub,
|
||||
union dmub_gpint_data_register reg)
|
||||
{
|
||||
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
|
||||
}
|
||||
|
||||
bool dmub_dcn42_is_gpint_acked(struct dmub_srv *dmub,
|
||||
union dmub_gpint_data_register reg)
|
||||
{
|
||||
union dmub_gpint_data_register test;
|
||||
|
||||
reg.bits.status = 0;
|
||||
test.all = REG_READ(DMCUB_GPINT_DATAIN1);
|
||||
|
||||
return test.all == reg.all;
|
||||
}
|
||||
|
||||
uint32_t dmub_dcn42_get_gpint_response(struct dmub_srv *dmub)
|
||||
{
|
||||
return REG_READ(DMCUB_SCRATCH7);
|
||||
}
|
||||
|
||||
uint32_t dmub_dcn42_get_gpint_dataout(struct dmub_srv *dmub)
|
||||
{
|
||||
uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
|
||||
|
||||
REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
|
||||
|
||||
REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
|
||||
REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
|
||||
REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
|
||||
|
||||
REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
|
||||
|
||||
return dataout;
|
||||
}
|
||||
|
||||
uint32_t dmub_dcn42_get_outbox0_wptr(struct dmub_srv *dmub)
|
||||
{
|
||||
return REG_READ(DMCUB_OUTBOX0_WPTR);
|
||||
}
|
||||
|
||||
void dmub_dcn42_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
|
||||
{
|
||||
REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
|
||||
}
|
||||
|
||||
uint32_t dmub_dcn42_get_current_time(struct dmub_srv *dmub)
|
||||
{
|
||||
return REG_READ(DMCUB_TIMER_CURRENT);
|
||||
}
|
||||
|
||||
void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub)
|
||||
{
|
||||
uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset, is_pwait;
|
||||
uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
|
||||
struct dmub_timeout_info timeout = {0};
|
||||
|
||||
if (!dmub)
|
||||
return;
|
||||
|
||||
/* timeout data filled externally, cache before resetting memory */
|
||||
timeout = dmub->debug.timeout_info;
|
||||
memset(&dmub->debug, 0, sizeof(dmub->debug));
|
||||
dmub->debug.timeout_info = timeout;
|
||||
|
||||
dmub->debug.dmcub_version = dmub->fw_version;
|
||||
|
||||
dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
|
||||
dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
|
||||
dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
|
||||
dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
|
||||
dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
|
||||
dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
|
||||
dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
|
||||
dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
|
||||
dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
|
||||
dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
|
||||
dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
|
||||
dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
|
||||
dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
|
||||
dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
|
||||
dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
|
||||
dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
|
||||
dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);
|
||||
|
||||
dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
|
||||
dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
|
||||
dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
|
||||
|
||||
dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
|
||||
dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
|
||||
dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
|
||||
|
||||
dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
|
||||
dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
|
||||
dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
|
||||
|
||||
dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);
|
||||
dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);
|
||||
dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
|
||||
|
||||
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
|
||||
dmub->debug.is_dmcub_enabled = is_dmub_enabled;
|
||||
|
||||
REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
|
||||
dmub->debug.is_pwait = is_pwait;
|
||||
|
||||
REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
|
||||
dmub->debug.is_dmcub_soft_reset = is_soft_reset;
|
||||
|
||||
REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
|
||||
dmub->debug.is_dmcub_secure_reset = is_sec_reset;
|
||||
|
||||
REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
|
||||
dmub->debug.is_traceport_en = is_traceport_enabled;
|
||||
|
||||
REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
|
||||
dmub->debug.is_cw0_enabled = is_cw0_enabled;
|
||||
|
||||
REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
|
||||
dmub->debug.is_cw6_enabled = is_cw6_enabled;
|
||||
|
||||
dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
|
||||
}
|
||||
|
||||
bool dmub_dcn42_get_preos_fw_info(struct dmub_srv *dmub)
|
||||
{
|
||||
uint64_t region3_cw5_offset;
|
||||
uint32_t top_addr, top_addr_enable, offset_low;
|
||||
uint32_t offset_high, base_addr, fw_version;
|
||||
bool is_vbios_fw = false;
|
||||
|
||||
memset(&dmub->preos_info, 0, sizeof(dmub->preos_info));
|
||||
|
||||
fw_version = REG_READ(DMCUB_SCRATCH1);
|
||||
is_vbios_fw = ((fw_version >> 6) & 0x01) ? true : false;
|
||||
if (!is_vbios_fw)
|
||||
return false;
|
||||
|
||||
dmub->preos_info.boot_status = REG_READ(DMCUB_SCRATCH0);
|
||||
dmub->preos_info.fw_version = REG_READ(DMCUB_SCRATCH1);
|
||||
dmub->preos_info.boot_options = REG_READ(DMCUB_SCRATCH14);
|
||||
REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS,
|
||||
DMCUB_REGION3_CW5_ENABLE, &top_addr_enable);
|
||||
if (top_addr_enable) {
|
||||
dmub_dcn42_get_fb_base_offset(dmub,
|
||||
&dmub->preos_info.fb_base, &dmub->preos_info.fb_offset);
|
||||
offset_low = REG_READ(DMCUB_REGION3_CW5_OFFSET);
|
||||
offset_high = REG_READ(DMCUB_REGION3_CW5_OFFSET_HIGH);
|
||||
region3_cw5_offset = ((uint64_t)offset_high << 32) | offset_low;
|
||||
dmub->preos_info.trace_buffer_phy_addr = region3_cw5_offset
|
||||
- dmub->preos_info.fb_base + dmub->preos_info.fb_offset;
|
||||
|
||||
REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS,
|
||||
DMCUB_REGION3_CW5_TOP_ADDRESS, &top_addr);
|
||||
base_addr = REG_READ(DMCUB_REGION3_CW5_BASE_ADDRESS) & 0x1FFFFFFF;
|
||||
dmub->preos_info.trace_buffer_size =
|
||||
(top_addr > base_addr) ? (top_addr - base_addr + 1) : 0;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void dmub_dcn42_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp)
|
||||
{
|
||||
REG_WRITE(DMCUB_REG_OUTBOX0_RSP, *rsp);
|
||||
}
|
||||
|
||||
uint32_t dmub_dcn42_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub)
|
||||
{
|
||||
uint32_t status;
|
||||
|
||||
REG_GET(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT, &status);
|
||||
return status;
|
||||
}
|
||||
171
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h
Normal file
171
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h
Normal file
|
|
@ -0,0 +1,171 @@
|
|||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright 2026 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DMUB_DCN42_H_
|
||||
#define _DMUB_DCN42_H_
|
||||
|
||||
#include "dmub_dcn35.h"
|
||||
#include "dmub_dcn401.h"
|
||||
|
||||
|
||||
struct dmub_srv;
|
||||
|
||||
/* DCN42 register definitions. */
|
||||
|
||||
#define DMUB_DCN42_REGS() \
|
||||
DMUB_DCN35_REGS() \
|
||||
DMUB_SR(DMCUB_INTERRUPT_STATUS) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_RDY) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG0) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG1) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG2) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG3) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG4) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG5) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG6) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG7) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG8) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG9) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG10) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG11) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG12) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG13) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_MSG14) \
|
||||
DMUB_SR(DMCUB_REG_INBOX0_RSP) \
|
||||
DMUB_SR(DMCUB_REG_OUTBOX0_RDY) \
|
||||
DMUB_SR(DMCUB_REG_OUTBOX0_MSG0) \
|
||||
DMUB_SR(DMCUB_REG_OUTBOX0_RSP) \
|
||||
DMUB_SR(HOST_INTERRUPT_CSR)
|
||||
|
||||
#define DMUB_DCN42_FIELDS() \
|
||||
DMUB_DCN35_FIELDS() \
|
||||
DMUB_SF(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT) \
|
||||
DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK) \
|
||||
DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT) \
|
||||
DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN) \
|
||||
DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK) \
|
||||
DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT) \
|
||||
DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN)
|
||||
|
||||
struct dmub_srv_dcn42_reg_offset {
|
||||
#define DMUB_SR(reg) uint32_t reg;
|
||||
DMUB_DCN42_REGS()
|
||||
DMCUB_INTERNAL_REGS()
|
||||
#undef DMUB_SR
|
||||
};
|
||||
|
||||
struct dmub_srv_dcn42_reg_shift {
|
||||
#define DMUB_SF(reg, field) uint8_t reg##__##field;
|
||||
DMUB_DCN42_FIELDS()
|
||||
#undef DMUB_SF
|
||||
};
|
||||
|
||||
struct dmub_srv_dcn42_reg_mask {
|
||||
#define DMUB_SF(reg, field) uint32_t reg##__##field;
|
||||
DMUB_DCN42_FIELDS()
|
||||
#undef DMUB_SF
|
||||
};
|
||||
|
||||
struct dmub_srv_dcn42_regs {
|
||||
struct dmub_srv_dcn42_reg_offset offset;
|
||||
struct dmub_srv_dcn42_reg_mask mask;
|
||||
struct dmub_srv_dcn42_reg_shift shift;
|
||||
};
|
||||
|
||||
/* Function declarations */
|
||||
|
||||
/* Initialization and configuration */
|
||||
void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);
|
||||
void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);
|
||||
void dmub_dcn42_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
|
||||
void dmub_dcn42_configure_dmub_in_system_memory(struct dmub_srv *dmub);
|
||||
|
||||
/* Reset and control */
|
||||
void dmub_dcn42_reset(struct dmub_srv *dmub);
|
||||
void dmub_dcn42_reset_release(struct dmub_srv *dmub);
|
||||
|
||||
/* Firmware loading */
|
||||
void dmub_dcn42_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1);
|
||||
void dmub_dcn42_backdoor_load_zfb_mode(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1);
|
||||
void dmub_dcn42_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6);
|
||||
|
||||
/* Mailbox operations - Inbox1 */
|
||||
void dmub_dcn42_setup_mailbox(struct dmub_srv *dmub, const struct dmub_region *inbox1);
|
||||
uint32_t dmub_dcn42_get_inbox1_wptr(struct dmub_srv *dmub);
|
||||
uint32_t dmub_dcn42_get_inbox1_rptr(struct dmub_srv *dmub);
|
||||
void dmub_dcn42_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
|
||||
|
||||
/* Mailbox operations - Outbox1 */
|
||||
void dmub_dcn42_setup_out_mailbox(struct dmub_srv *dmub, const struct dmub_region *outbox1);
|
||||
uint32_t dmub_dcn42_get_outbox1_wptr(struct dmub_srv *dmub);
|
||||
void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
|
||||
|
||||
/* Mailbox operations - Outbox0 */
|
||||
void dmub_dcn42_setup_outbox0(struct dmub_srv *dmub, const struct dmub_region *outbox0);
|
||||
uint32_t dmub_dcn42_get_outbox0_wptr(struct dmub_srv *dmub);
|
||||
void dmub_dcn42_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
|
||||
|
||||
/* Mailbox operations - Inbox0 */
|
||||
void dmub_dcn42_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);
|
||||
void dmub_dcn42_clear_inbox0_ack_register(struct dmub_srv *dmub);
|
||||
uint32_t dmub_dcn42_read_inbox0_ack_register(struct dmub_srv *dmub);
|
||||
|
||||
/* REG Inbox0/Outbox0 operations */
|
||||
void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, union dmub_rb_cmd *cmd);
|
||||
uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub);
|
||||
void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub, union dmub_rb_cmd *cmd);
|
||||
void dmub_dcn42_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);
|
||||
void dmub_dcn42_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);
|
||||
void dmub_dcn42_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable);
|
||||
|
||||
void dmub_dcn42_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub);
|
||||
void dmub_dcn42_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg);
|
||||
void dmub_dcn42_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp);
|
||||
uint32_t dmub_dcn42_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub);
|
||||
void dmub_dcn42_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable);
|
||||
uint32_t dmub_dcn42_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub);
|
||||
|
||||
/* GPINT operations */
|
||||
void dmub_dcn42_set_gpint(struct dmub_srv *dmub, union dmub_gpint_data_register reg);
|
||||
bool dmub_dcn42_is_gpint_acked(struct dmub_srv *dmub, union dmub_gpint_data_register reg);
|
||||
uint32_t dmub_dcn42_get_gpint_response(struct dmub_srv *dmub);
|
||||
uint32_t dmub_dcn42_get_gpint_dataout(struct dmub_srv *dmub);
|
||||
|
||||
/* Status and detection */
|
||||
bool dmub_dcn42_is_hw_init(struct dmub_srv *dmub);
|
||||
bool dmub_dcn42_is_supported(struct dmub_srv *dmub);
|
||||
bool dmub_dcn42_is_hw_powered_up(struct dmub_srv *dmub);
|
||||
bool dmub_dcn42_should_detect(struct dmub_srv *dmub);
|
||||
|
||||
|
||||
/* Firmware boot status and options */
|
||||
union dmub_fw_boot_status dmub_dcn42_get_fw_boot_status(struct dmub_srv *dmub);
|
||||
union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub);
|
||||
|
||||
/* Timing and diagnostics */
|
||||
uint32_t dmub_dcn42_get_current_time(struct dmub_srv *dmub);
|
||||
void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub);
|
||||
bool dmub_dcn42_get_preos_fw_info(struct dmub_srv *dmub);
|
||||
|
||||
#endif /* _DMUB_DCN42_H_ */
|
||||
Loading…
Reference in New Issue
Block a user