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media: imx355: Support 2 lane readout
The sensor supports 2 or 4 lane readout, but the driver only allowed for 4 lanes. Add 2 lane support. The clock tree only supports single PLL mode to feed both IOP (MIPI) and IVT (Pixel array). 2 lane mode supports a MIPI link frequency of up to 445MHz (890Mbit/s) cf 360MHz (720Mbit/s) for 4lane. Update clock setup and pixel rates to match. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
This commit is contained in:
Dave Stevenson
Sakari Ailus
parent
b8d87e9bdb
commit
7c3aad6fba
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@ -27,11 +27,14 @@
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#define IMX355_REG_CHIP_ID CCI_REG16(0x0016)
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#define IMX355_CHIP_ID 0x0355
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#define IMX355_REG_LANE_SEL CCI_REG8(0x0114)
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/* PLL registers that depend on the external clock frequency */
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#define IMX355_REG_EXTCLK_FREQ CCI_REG16(0x0136)
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#define IMX355_REG_PLL_OP_PREDIV CCI_REG8(0x030d)
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#define IMX355_REG_PLL_OP_MUL CCI_REG16(0x030e)
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#define IMX355_REG_PLL_IVT_PCK_DIV CCI_REG8(0x0301)
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#define IMX355_REG_PLL_IVT_SYSCK_DIV CCI_REG8(0x0303)
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#define IMX355_PLL_OP_PREDIV 2
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#define IMX355_PLL_IVT_PCK_DIV 5
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@ -80,6 +83,8 @@
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#define IMX355_TEST_PATTERN_GRAY_COLOR_BARS 3
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#define IMX355_TEST_PATTERN_PN9 4
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#define IMX355_REG_REQ_LINK_BIT_RATE CCI_REG16(0x0820)
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#define IMX355_REG_BINNING_MODE CCI_REG8(0x0900)
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#define IMX355_REG_BINNING_TYPE CCI_REG8(0x0901)
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#define IMX355_REG_BINNING_WEIGHTING CCI_REG8(0x0902)
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@ -87,9 +92,6 @@
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/* Flip Control */
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#define IMX355_REG_ORIENTATION CCI_REG8(0x0101)
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/* number of data lanes */
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#define IMX355_DATA_LANES 4
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#define IMX355_PIXEL_ARRAY_TOP 0
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#define IMX355_PIXEL_ARRAY_LEFT 0
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#define IMX355_PIXEL_ARRAY_WIDTH 3280
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@ -120,30 +122,38 @@ struct imx355_mode {
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struct imx355_clk_params {
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u32 ext_clk;
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u16 extclk_freq; /* External clock (MHz) in 8.8 fixed point) */
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u16 pll_op_mpy; /* OP system PLL multiplier */
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u16 extclk_freq; /* External clock (MHz) in 8.8 fixed point) */
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u16 pll_op_mpy[2]; /* OP system PLL multiplier */
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u8 pll_op_prediv[2]; /* OP system pre PLL d */
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};
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/*
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* The clock tree is in single PLL mode, so PREDIV_VT and MPY_IVT do nothing.
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* All modes use the same PLL setup for OP, with IOPCK being 720MHz.
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* In 4 lane mode the MIPI rate is 360Mhz (720Mbit/s) and pixel rate is
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* 288MPix/s.
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* In 2 lane mode the MIPI rate is 444MHz (888Mbit/s) and pixel rate
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* 177.6MPix/s with a 24MHz clock, and 441.6MHz (883.2Mbit/s) and 176.6MPix/s
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* with a 19.2MHz clock.
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*/
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static const struct imx355_clk_params imx355_clk_params[] = {
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{
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.ext_clk = 19200000,
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.extclk_freq = 0x1333, /* 19.2 MHz */
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.pll_op_mpy = 75, /* 19.2 / 2 * 75 = 720 MHz */
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.extclk_freq = 0x1333,
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.pll_op_mpy = { 75, 92 },
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.pll_op_prediv = { 2, 2 }
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},
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{
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.ext_clk = 24000000,
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.extclk_freq = 0x1800, /* 24.0 MHz */
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.pll_op_mpy = 60, /* 24.0 / 2 * 60 = 720 MHz */
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.extclk_freq = 0x1800,
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.pll_op_mpy = { 60, 111 },
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.pll_op_prediv = { 2, 3 }
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},
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};
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struct imx355_hwcfg {
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s64 link_freq_menu;
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unsigned long link_freq_bitmap;
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unsigned int num_lanes;
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};
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struct imx355 {
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@ -239,7 +249,6 @@ static const struct cci_reg_sequence imx355_global_regs[] = {
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{ CCI_REG8(0x305a), 0x00 },
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{ CCI_REG8(0x0112), 0x0a },
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{ CCI_REG8(0x0113), 0x0a },
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{ CCI_REG8(0x0114), 0x03 },
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{ IMX355_REG_PLL_IVT_PCK_DIV, IMX355_PLL_IVT_PCK_DIV },
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{ CCI_REG8(0x0303), 0x01 },
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{ CCI_REG8(0x0305), 0x02 },
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@ -250,8 +259,6 @@ static const struct cci_reg_sequence imx355_global_regs[] = {
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{ CCI_REG8(0x0310), 0x00 },
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{ CCI_REG8(0x0220), 0x00 },
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{ CCI_REG8(0x0222), 0x01 },
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{ CCI_REG8(0x0820), 0x0b },
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{ CCI_REG8(0x0821), 0x40 },
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{ CCI_REG8(0x3088), 0x04 },
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{ CCI_REG8(0x6813), 0x02 },
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{ CCI_REG8(0x6835), 0x07 },
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@ -817,6 +824,7 @@ imx355_set_pad_format(struct v4l2_subdev *sd,
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__v4l2_ctrl_modify_range(imx355->vblank, IMX355_VBLANK_MIN,
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height, 1, vblank_def);
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__v4l2_ctrl_s_ctrl(imx355->vblank, vblank_def);
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h_blank = mode->llp - imx355->cur_mode->width;
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/*
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* Currently hblank is not changeable.
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@ -880,6 +888,8 @@ static int imx355_start_streaming(struct imx355 *imx355)
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{
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const struct imx355_reg_list *reg_list;
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const struct imx355_mode *mode;
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int lane_idx = imx355->hwcfg->num_lanes == 4 ? 0 : 1;
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u64 link_bitrate;
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u8 binning_mode;
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int ret = 0;
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@ -915,7 +925,21 @@ static int imx355_start_streaming(struct imx355 *imx355)
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cci_write(imx355->regmap, IMX355_REG_EXTCLK_FREQ,
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imx355->clk_params->extclk_freq, &ret);
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cci_write(imx355->regmap, IMX355_REG_PLL_OP_MUL,
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imx355->clk_params->pll_op_mpy, &ret);
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imx355->clk_params->pll_op_mpy[lane_idx], &ret);
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cci_write(imx355->regmap, IMX355_REG_PLL_OP_PREDIV,
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imx355->clk_params->pll_op_prediv[lane_idx], &ret);
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cci_write(imx355->regmap, IMX355_REG_PLL_IVT_SYSCK_DIV,
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lane_idx ? 2 : 1, &ret);
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/* Set MIPI configuration */
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cci_write(imx355->regmap, IMX355_REG_LANE_SEL,
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imx355->hwcfg->num_lanes - 1, &ret);
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link_bitrate = imx355->link_freq->qmenu_int[imx355->link_freq->val] *
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imx355->hwcfg->num_lanes * 2;
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do_div(link_bitrate, 1000000);
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cci_write(imx355->regmap, IMX355_REG_REQ_LINK_BIT_RATE, link_bitrate,
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&ret);
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/* set digital gain control to all color mode */
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cci_write(imx355->regmap, IMX355_REG_DPGA_USE_GLOBAL_GAIN, 1, &ret);
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@ -1101,9 +1125,9 @@ static int imx355_init_controls(struct imx355 *imx355)
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imx355->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
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/* pixel_rate = link_freq * 2 * nr_of_lanes / bits_per_sample */
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pixel_rate = imx355->hwcfg->link_freq_menu * 2 * 4;
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pixel_rate = imx355->hwcfg->link_freq_menu * 2 * imx355->hwcfg->num_lanes;
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do_div(pixel_rate, 10);
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/* By default, PIXEL_RATE is read only */
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v4l2_ctrl_new_std(ctrl_hdlr, &imx355_ctrl_ops, V4L2_CID_PIXEL_RATE,
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pixel_rate, pixel_rate, 1, pixel_rate);
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@ -1186,6 +1210,7 @@ static struct imx355_hwcfg *imx355_get_hwcfg(struct imx355 *imx355)
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const struct imx355_clk_params *clk = imx355->clk_params;
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struct fwnode_handle *ep;
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struct fwnode_handle *fwnode = dev_fwnode(dev);
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int lane_idx;
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int ret;
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if (!fwnode)
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@ -1203,11 +1228,15 @@ static struct imx355_hwcfg *imx355_get_hwcfg(struct imx355 *imx355)
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if (!cfg)
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goto out_err;
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if (bus_cfg.bus.mipi_csi2.num_data_lanes != IMX355_DATA_LANES)
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if (bus_cfg.bus.mipi_csi2.num_data_lanes != 2 &&
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bus_cfg.bus.mipi_csi2.num_data_lanes != 4)
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goto out_err;
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cfg->link_freq_menu = (clk->ext_clk * clk->pll_op_mpy) /
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(IMX355_PLL_OP_PREDIV * 2);
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cfg->num_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
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lane_idx = cfg->num_lanes == 4 ? 0 : 1;
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cfg->link_freq_menu = (clk->ext_clk * clk->pll_op_mpy[lane_idx]) /
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(clk->pll_op_prediv[lane_idx] * 2);
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ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies,
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bus_cfg.nr_of_link_frequencies,
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&cfg->link_freq_menu, 1,
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