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clk: qcom: dispcc-sm8450: Add SM8475 support

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Add support to the SM8475 display clock controller by extending the
SM8450 display clock controller, which is almost identical but has
some minor differences.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240818204348.197788-5-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Danila Tikhonov 2024-08-18 23:43:42 +03:00 committed by Bjorn Andersson
parent 20e06dc8c9
commit 7c0e8764dc
2 changed files with 64 additions and 4 deletions
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2
drivers/clk/qcom/Kconfig
View File

@ -952,7 +952,7 @@ config SM_DISPCC_8450
depends on SM_GCC_8450
help
Support for the display clock controller on Qualcomm Technologies, Inc
SM8450 devices.
SM8450 or SM8475 devices.
Say Y if you want to support display devices and functionality such as
splash screen.

66
drivers/clk/qcom/dispcc-sm8450.c
View File

@ -85,6 +85,29 @@ static const struct alpha_pll_config disp_cc_pll0_config = {
.user_ctl_hi_val = 0x00000805,
};
static const struct alpha_pll_config sm8475_disp_cc_pll0_config = {
.l = 0xd,
.alpha = 0x6492,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_init_data sm8475_disp_cc_pll0_init = {
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_reset_lucid_ole_ops,
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_evo_vco,
@ -112,6 +135,29 @@ static const struct alpha_pll_config disp_cc_pll1_config = {
.user_ctl_hi_val = 0x00000805,
};
static const struct alpha_pll_config sm8475_disp_cc_pll1_config = {
.l = 0x1f,
.alpha = 0x4000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_init_data sm8475_disp_cc_pll1_init = {
.name = "disp_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_reset_lucid_ole_ops,
};
static struct clk_alpha_pll disp_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_evo_vco,
@ -1746,6 +1792,7 @@ static struct qcom_cc_desc disp_cc_sm8450_desc = {
static const struct of_device_id disp_cc_sm8450_match_table[] = {
{ .compatible = "qcom,sm8450-dispcc" },
{ .compatible = "qcom,sm8475-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sm8450_match_table);
@ -1769,8 +1816,21 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev)
goto err_put_rpm;
}
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-dispcc")) {
/* Update DISPCC PLL0 */
disp_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
disp_cc_pll0.clkr.hw.init = &sm8475_disp_cc_pll0_init;
/* Update DISPCC PLL1 */
disp_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
disp_cc_pll1.clkr.hw.init = &sm8475_disp_cc_pll1_init;
clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &sm8475_disp_cc_pll0_config);
clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &sm8475_disp_cc_pll1_config);
} else {
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
}
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
@ -1802,5 +1862,5 @@ static struct platform_driver disp_cc_sm8450_driver = {
module_platform_driver(disp_cc_sm8450_driver);
MODULE_DESCRIPTION("QTI DISPCC SM8450 Driver");
MODULE_DESCRIPTION("QTI DISPCC SM8450 / SM8475 Driver");
MODULE_LICENSE("GPL");