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drm/i915/vrr: Add function to check if DC Balance Possible

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Add a function that checks if DC Balance enabling is possible on the
requested PIPE. Apart from the DISPLAY_VER check, account for current
firmware limitations, which only allow DC Balance on PIPE A and PIPE B.

v2: Rephrased commit message. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251223104542.2688548-9-mitulkumar.ajitkumar.golani@intel.com
This commit is contained in:
Mitul Golani 2025-12-23 16:15:30 +05:30 committed by Ankit Nautiyal
parent 2873c8eaa1
commit 7bf11bc2f7
1 changed files with 17 additions and 2 deletions
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19
drivers/gpu/drm/i915/display/intel_vrr.c
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@ -351,13 +351,28 @@ int intel_vrr_compute_vmax(struct intel_connector *connector,
return vmax;
}
static bool intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
/*
* FIXME: Currently Firmware supports DC Balancing on PIPE A
* and PIPE B. Account those limitation while computing DC
* Balance parameters.
*/
return (HAS_VRR_DC_BALANCE(display) &&
((pipe == PIPE_A) || (pipe == PIPE_B)));
}
static void
intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state)
{
int guardband_usec, adjustment_usec;
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
if (!HAS_VRR_DC_BALANCE(display) || !crtc_state->vrr.enable)
if (!intel_vrr_dc_balance_possible(crtc_state) || !crtc_state->vrr.enable)
return;
crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
@ -839,7 +854,7 @@ void intel_vrr_get_dc_balance_config(struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
if (!HAS_VRR_DC_BALANCE(display))
if (!intel_vrr_dc_balance_possible(crtc_state))
return;
reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));