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dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller

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These SoCs have 3 clock and reset controllers: Top, Matrix and LSP.
Clocks go from oscillator -> top -> matrix -> LSP, with a register in
top controlling most clocks that get passed to matrix and a register in
matrix controlling all the clocks that get passed to LSP.

Generally every device has two clocks (one work clock, and one that
connects it to the bus, I call it PCLK), two reset bits (I don't know
what the difference is - sometimes asserting one is enough to reset the
device, sometimes both need to be asserted). PCLK and WCLK are
controlled by individual gates. Some devices have a mux and/or a
divider for their work clock. Some devices, like the GPIO controller,
only have reset bits and no clocks.

The top clock controller is fed by a 26 MHz external oscillator and has 4
PLLs to generate other clock rates. ZTE's kernel mostly relies on the
boot ROM to set up PLLs, but one LTE-related PLL is not configured
on some boards. Therefore my driver contains code to program PLLs. It
produces identical settings as the boot ROM for the pre-programmed
frequencies.

Not all clocks will have an explicit user in the end. I am defining a
lot of them simply to shut them off. The boot loader sets up a few of
the proprietary timers, which will send regular IRQs (although the
kernel of course doesn't need to listen to them). I don't plan to add a
driver for the proprietary timer as I see no use for them - the ARM arch
timer works just fine. I will add a driver for the very similar
proprietary watchdog though.

The clock list in this patch is pretty complete but not exhaustive.
There are other bits that are enabled, but I couldn't deduce what they
are controlling by trial and error. Some of them seem to do nothing.
Others cause an instant hang of the board when disabled. It is quite
likely that a handful more clocks will be added in the future, but not a
large number.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
This commit is contained in:
Stefan Dösinger 2026-09-27 23:13:29 +03:00 committed by Brian Masney
parent 1dc3871ce7
commit 7bdc3c32d5
5 changed files with 240 additions and 0 deletions
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122
Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/zte,zx297520v3-topcrm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ZTE zx297520v3 SoC top clock and reset controller
maintainers:
- Stefan Dösinger <stefandoesinger@gmail.com>
description: |
The zx297520v3 top clock and reset controller generates clocks for core
devices on the board like the main bus, USB and timers. In addition to clocks
it has reset controls for peripherals, a global board reset, watchdog reset
controls and a USB status register.
The controller has two clock inputs: a 26 MHz and a 32 kHz external
oscillator. They need to be provided as input clocks. The controller provides
PLL output frequencies to downstream clock controllers.
The USB PHY is exposed as two PHYs, one for USB and another for HSIC. Note
that while the controls for both PHYs are always present, the PHYs themselves
may be absent. If this is the case the controller never signals that the
missing PHY is ready.
All available clocks are defined as preprocessor macros in the
"include/dt-bindings/clock/zte,zx297520v3-clk.h" header. The resets are
defined in the "include/dt-bindings/reset/zte,zx297520v3-reset.h" header. PHY
defines are found in "include/dt-bindings/phy/zte,zx297520v3-topcrm.h".
properties:
compatible:
items:
- const: zte,zx297520v3-topcrm
- const: syscon
reg:
maxItems: 1
clocks:
items:
- description: 26 MHz external oscillator
- description: 32 kHz external oscillator
clock-names:
items:
- const: osc26m
- const: osc32k
interrupts:
items:
- description: IRQ reporting USB connection
- description: IRQ reporting USB disconnection
- description: IRQ reporting HSIC connection
- description: IRQ reporting HSIC disconnection
interrupt-names:
items:
- const: usb-up
- const: usb-down
- const: hsic-up
- const: hsic-down
"#clock-cells":
const: 1
"#phy-cells":
const: 1
"#reset-cells":
const: 1
reboot:
type: object
$ref: /schemas/power/reset/syscon-reboot.yaml#
unevaluatedProperties: false
description:
Reboot method for the SoC.
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- interrupt-names
- reboot
- "#clock-cells"
- "#phy-cells"
- "#reset-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/zte,zx297520v3-reset.h>
#include <dt-bindings/phy/zte,zx297520v3-topcrm.h>
#include <dt-bindings/clock/zte,zx297520v3-clk.h>
clock-controller@13b000 {
compatible = "zte,zx297520v3-topcrm", "syscon";
reg = <0x0013b000 0x400>;
#clock-cells = <1>;
clocks = <&osc26m>, <&osc32k>;
clock-names = "osc26m", "osc32k";
interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "usb-up", "usb-down", "hsic-up", "hsic-down";
#phy-cells = <1>;
#reset-cells = <1>;
reboot {
compatible = "syscon-reboot";
mask = <0x1>;
offset = <0x0>;
value = <0x1>;
};
};

4
MAINTAINERS
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@ -3909,8 +3909,12 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Odd fixes
F: Documentation/arch/arm/zte/
F: Documentation/devicetree/bindings/arm/zte.yaml
F: Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml
F: arch/arm/boot/dts/zte/
F: arch/arm/mach-zte/
F: include/dt-bindings/clock/zte,zx297520v3-clk.h
F: include/dt-bindings/phy/zte,zx297520v3-topcrm.h
F: include/dt-bindings/reset/zte,zx297520v3-reset.h
ARM/ZYNQ ARCHITECTURE
M: Michal Simek <michal.simek@amd.com>

72
include/dt-bindings/clock/zte,zx297520v3-clk.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) Stefan Dösinger.
*/
#ifndef __DT_BINDINGS_CLOCK_ZX297520V3_H
#define __DT_BINDINGS_CLOCK_ZX297520V3_H
#define ZX297520V3_M0_WCLK 0
#define ZX297520V3_SRAM1_PCLK 1
#define ZX297520V3_SRAM2_PCLK 2
#define ZX297520V3_UART0_WCLK 3
#define ZX297520V3_UART0_PCLK 4
#define ZX297520V3_I2C0_WCLK 5
#define ZX297520V3_I2C0_PCLK 6
#define ZX297520V3_RTC_WCLK 7
#define ZX297520V3_RTC_PCLK 8
#define ZX297520V3_LPM_GSM_WCLK 9
#define ZX297520V3_LPM_GSM_PCLK 10
#define ZX297520V3_LPM_LTE_WCLK 11
#define ZX297520V3_LPM_LTE_PCLK 12
#define ZX297520V3_LPM_TD_WCLK 13
#define ZX297520V3_LPM_TD_PCLK 14
#define ZX297520V3_LPM_W_WCLK 15
#define ZX297520V3_LPM_W_PCLK 16
#define ZX297520V3_TIMER_T08_WCLK 17
#define ZX297520V3_TIMER_T08_PCLK 18
#define ZX297520V3_TIMER_T09_WCLK 19
#define ZX297520V3_TIMER_T09_PCLK 20
#define ZX297520V3_MPLL 21
#define ZX297520V3_MPLL_D5 22
#define ZX297520V3_DPLL 23
#define ZX297520V3_GPLL 24
#define ZX297520V3_GPLL_D2 25
#define ZX297520V3_GATED_OSC26M 26
#define ZX297520V3_PMM_WCLK 27
#define ZX297520V3_PMM_PCLK 28
#define ZX297520V3_OUT0_WCLK 29
#define ZX297520V3_OUT1_WCLK 30
#define ZX297520V3_OUT2_WCLK 31
#define ZX297520V3_OUT32K_WCLK 32
#define ZX297520V3_RMIIPHY_WCLK 33
#define ZX297520V3_TIMER_T12_WCLK 34
#define ZX297520V3_TIMER_T12_PCLK 35
#define ZX297520V3_TIMER_T13_WCLK 36
#define ZX297520V3_TIMER_T13_PCLK 37
#define ZX297520V3_TIMER_T14_WCLK 38
#define ZX297520V3_TIMER_T14_PCLK 39
#define ZX297520V3_TIMER_T15_WCLK 40
#define ZX297520V3_TIMER_T15_PCLK 41
#define ZX297520V3_TIMER_T16_WCLK 42
#define ZX297520V3_TIMER_T16_PCLK 43
#define ZX297520V3_TIMER_T17_WCLK 44
#define ZX297520V3_TIMER_T17_PCLK 45
#define ZX297520V3_WDT_T18_WCLK 46
#define ZX297520V3_WDT_T18_PCLK 47
#define ZX297520V3_USIM1_WCLK 48
#define ZX297520V3_USIM1_PCLK 49
#define ZX297520V3_AHB_WCLK 50
#define ZX297520V3_AHB_PCLK 51
#define ZX297520V3_USB_WCLK 52
#define ZX297520V3_USB_PCLK 53
#define ZX297520V3_HSIC_WCLK 54
#define ZX297520V3_HSIC_PCLK 55
#define ZX297520V3_GSM_32K 56
#define ZX297520V3_GSM_26M 57
#define ZX297520V3_GSM_48M 58
#define ZX297520V3_GSM_104M 59
#define ZX297520V3_GSM_156M 60
#define ZX297520V3_ABB_WCLK 61
#endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */

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include/dt-bindings/phy/zte,zx297520v3-topcrm.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) Stefan Dösinger.
*/
#ifndef __DT_BINDINGS_PHY_ZTE_ZX297520V3_TOPCRM_H
#define __DT_BINDINGS_PHY_ZTE_ZX297520V3_TOPCRM_H
#define ZX297520V3_USB_PHY 0
#define ZX297520V3_HSIC_PHY 1
#endif /* __DT_BINDINGS_PHY_ZTE_ZX297520V3_TOPCRM_H */

30
include/dt-bindings/reset/zte,zx297520v3-reset.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) Stefan Dösinger.
*/
#ifndef __DT_BINDINGS_RESET_ZX297520V3_H
#define __DT_BINDINGS_RESET_ZX297520V3_H
#define ZX297520V3_ZSP_CORE_RESET 0
#define ZX297520V3_UART0_RESET 1
#define ZX297520V3_I2C0_RESET 2
#define ZX297520V3_RTC_RESET 3
#define ZX297520V3_TIMER_T08_RESET 4
#define ZX297520V3_TIMER_T09_RESET 5
#define ZX297520V3_PMM_RESET 6
#define ZX297520V3_GPIO_RESET 7
#define ZX297520V3_GPIO8_RESET 8
#define ZX297520V3_TIMER_T12_RESET 9
#define ZX297520V3_TIMER_T13_RESET 10
#define ZX297520V3_TIMER_T14_RESET 11
#define ZX297520V3_TIMER_T15_RESET 12
#define ZX297520V3_TIMER_T16_RESET 13
#define ZX297520V3_TIMER_T17_RESET 14
#define ZX297520V3_WDT_T18_RESET 15
#define ZX297520V3_USIM1_RESET 16
#define ZX297520V3_AHB_RESET 17
#define ZX297520V3_USB_RESET 18
#define ZX297520V3_HSIC_RESET 19
#endif /* __DT_BINDINGS_RESET_ZX297520V3_H */