diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml index 5a99d9b9635e..c20625b8425e 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -14,16 +14,21 @@ description: | RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with up to four data lanes. -allOf: - - $ref: /schemas/display/dsi-controller.yaml# - properties: compatible: - items: + oneOf: + - items: + - enum: + - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} + - renesas,r9a07g054-mipi-dsi # RZ/V2L + - const: renesas,rzg2l-mipi-dsi + + - items: + - const: renesas,r9a09g056-mipi-dsi # RZ/V2N + - const: renesas,r9a09g057-mipi-dsi + - enum: - - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} - - renesas,r9a07g054-mipi-dsi # RZ/V2L - - const: renesas,rzg2l-mipi-dsi + - renesas,r9a09g057-mipi-dsi # RZ/V2H(P) reg: maxItems: 1 @@ -49,34 +54,56 @@ properties: - const: debug clocks: - items: - - description: DSI D-PHY PLL multiplied clock - - description: DSI D-PHY system clock - - description: DSI AXI bus clock - - description: DSI Register access clock - - description: DSI Video clock - - description: DSI D-PHY Escape mode transmit clock + oneOf: + - items: + - description: DSI D-PHY PLL multiplied clock + - description: DSI D-PHY system clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock + - items: + - description: DSI D-PHY PLL reference clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock clock-names: - items: - - const: pllclk - - const: sysclk - - const: aclk - - const: pclk - - const: vclk - - const: lpclk + oneOf: + - items: + - const: pllclk + - const: sysclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk + - items: + - const: pllrefclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk resets: - items: - - description: MIPI_DSI_CMN_RSTB - - description: MIPI_DSI_ARESET_N - - description: MIPI_DSI_PRESET_N + oneOf: + - items: + - description: MIPI_DSI_CMN_RSTB + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N + - items: + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N reset-names: - items: - - const: rst - - const: arst - - const: prst + oneOf: + - items: + - const: rst + - const: arst + - const: prst + - items: + - const: arst + - const: prst power-domains: maxItems: 1 @@ -130,6 +157,41 @@ required: unevaluatedProperties: false +allOf: + - $ref: ../dsi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-mipi-dsi + then: + properties: + clocks: + maxItems: 5 + + clock-names: + maxItems: 5 + + resets: + maxItems: 2 + + reset-names: + maxItems: 2 + else: + properties: + clocks: + minItems: 6 + + clock-names: + minItems: 6 + + resets: + minItems: 3 + + reset-names: + minItems: 3 + examples: - | #include diff --git a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml index 2219d3d4ac43..f641efaeb8b3 100644 --- a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml +++ b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml @@ -4,14 +4,16 @@ $id: http://devicetree.org/schemas/display/panel/lg,sw43408.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: LG SW43408 1080x2160 DSI panel +title: LG SW43408 AMOLED DDIC maintainers: - Casey Connolly description: - This panel is used on the Pixel 3, it is a 60hz OLED panel which - required DSC (Display Stream Compression) and has rounded corners. + The SW43408 is display driver IC with connected panel. + + LG LH546WF1-ED01 panel is used on the Pixel 3, it is a 60hz OLED panel + which required DSC (Display Stream Compression) and has rounded corners. allOf: - $ref: panel-common.yaml# @@ -19,6 +21,9 @@ allOf: properties: compatible: items: + - enum: + # LG 5.46 inch, 1080x2160 pixels, 18:9 ratio + - lg,sw43408-lh546wf1-ed01 - const: lg,sw43408 reg: @@ -46,7 +51,7 @@ examples: #size-cells = <0>; panel@0 { - compatible = "lg,sw43408"; + compatible = "lg,sw43408-lh546wf1-ed01", "lg,sw43408"; reg = <0>; vddi-supply = <&vreg_l14a_1p88>; diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml index 8d668979b62d..2f90c887b7b8 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml @@ -55,6 +55,8 @@ properties: - panasonic,vvx10f004b00 # Panasonic 10" WUXGA TFT LCD panel - panasonic,vvx10f034n00 + # Samsung ltl106hl02 10.6" Full HD TFT LCD panel + - samsung,ltl106hl02-001 # Samsung s6e3fa7 1080x2220 based AMS559NK06 AMOLED panel - samsung,s6e3fa7-ams559nk06 # Shangai Top Display Optoelectronics 7" TL070WSH30 1024x600 TFT LCD panel diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 24e277b19094..fc244fbb5a54 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -154,6 +154,8 @@ properties: - hannstar,hsd070pww1 # HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel - hannstar,hsd100pxn1 + # HannStar Display Corp. HSD156JUW2 15.6" FHD (1920x1080) TFT LCD panel + - hannstar,hsd156juw2 # Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel - hit,tx23d38vm0caa # Innolux AT043TN24 4.3" WQVGA TFT LCD panel diff --git a/Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml b/Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml index d48354fb52ea..fd4388f5fb11 100644 --- a/Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml +++ b/Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml @@ -6,11 +6,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung S6E3FC2X01 AMOLED DDIC -description: The S6E3FC2X01 is display driver IC with connected panel. - maintainers: - David Heidelberg +description: The S6E3FC2X01 is display driver IC with connected panel. + allOf: - $ref: panel-common.yaml# @@ -25,25 +25,21 @@ properties: reg: maxItems: 1 - reset-gpios: true - - port: true - - vddio-supply: - description: VDD regulator + poc-supply: + description: POC regulator vci-supply: description: VCI regulator - poc-supply: - description: POC regulator + vddio-supply: + description: VDD regulator required: - compatible - reset-gpios - - vddio-supply - - vci-supply - poc-supply + - vci-supply + - vddio-supply unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml index 9d096856a79a..29716764413a 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml @@ -23,6 +23,7 @@ properties: - rockchip,rk3228-dw-hdmi - rockchip,rk3288-dw-hdmi - rockchip,rk3328-dw-hdmi + - rockchip,rk3368-dw-hdmi - rockchip,rk3399-dw-hdmi - rockchip,rk3568-dw-hdmi diff --git a/Documentation/devicetree/bindings/display/sitronix,st7571.yaml b/Documentation/devicetree/bindings/display/sitronix,st7571.yaml index b83721eb4b7f..1931a47c4217 100644 --- a/Documentation/devicetree/bindings/display/sitronix,st7571.yaml +++ b/Documentation/devicetree/bindings/display/sitronix,st7571.yaml @@ -76,3 +76,28 @@ examples: }; }; }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + + display@0 { + compatible = "sitronix,st7571"; + reg = <0>; + reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + width-mm = <37>; + height-mm = <27>; + + panel-timing { + hactive = <128>; + vactive = <96>; + hback-porch = <0>; + vback-porch = <0>; + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/sitronix,st7920.yaml b/Documentation/devicetree/bindings/display/sitronix,st7920.yaml new file mode 100644 index 000000000000..c4f006fc41e1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/sitronix,st7920.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/sitronix,st7920.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sitronix ST7920 LCD Display Controllers + +maintainers: + - Iker Pedrosa + +description: + The Sitronix ST7920 is a controller for monochrome dot-matrix graphical LCDs, + most commonly used for 128x64 pixel displays. + +properties: + compatible: + const: sitronix,st7920 + + reg: + maxItems: 1 + + vdd-supply: + description: Regulator that provides 5V Vdd power supply + + reset-gpios: + maxItems: 1 + + spi-max-frequency: + maximum: 600000 + +required: + - compatible + - reg + - spi-max-frequency + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + display@0 { + compatible = "sitronix,st7920"; + reg = <0>; + vdd-supply = <®_5v>; + reset-gpios = <&gpio 25 GPIO_ACTIVE_LOW>; + spi-max-frequency = <600000>; + spi-cs-high; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index dc731d37c8fe..bdbe32ddcedb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8201,6 +8201,9 @@ S: Maintained F: Documentation/devicetree/bindings/display/sitronix,st7567.yaml F: Documentation/devicetree/bindings/display/sitronix,st7571.yaml F: drivers/gpu/drm/sitronix/st7571-i2c.c +F: drivers/gpu/drm/sitronix/st7571-spi.c +F: drivers/gpu/drm/sitronix/st7571.c +F: drivers/gpu/drm/sitronix/st7571.h DRM DRIVER FOR SITRONIX ST7701 PANELS M: Jagan Teki @@ -8223,6 +8226,13 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: Documentation/devicetree/bindings/display/sitronix,st7735r.yaml F: drivers/gpu/drm/sitronix/st7735r.c +DRM DRIVER FOR SITRONIX ST7920 LCD DISPLAYS +M: Iker Pedrosa +S: Maintained +T: git https://gitlab.freedesktop.org/drm/misc/kernel.git +F: Documentation/devicetree/bindings/display/sitronix,st7920.yaml +F: drivers/gpu/drm/sitronix/st7920.c + DRM DRIVER FOR SOLOMON SSD130X OLED DISPLAYS M: Javier Martinez Canillas S: Maintained diff --git a/drivers/accel/amdxdna/Makefile b/drivers/accel/amdxdna/Makefile index 6344aaf523fa..3fa0e74fd8f5 100644 --- a/drivers/accel/amdxdna/Makefile +++ b/drivers/accel/amdxdna/Makefile @@ -18,7 +18,6 @@ amdxdna-y := \ amdxdna_sysfs.o \ amdxdna_ubuf.o \ npu1_regs.o \ - npu2_regs.o \ npu4_regs.o \ npu5_regs.o \ npu6_regs.o diff --git a/drivers/accel/amdxdna/aie2_ctx.c b/drivers/accel/amdxdna/aie2_ctx.c index 42d876a427c5..5511ab2ef242 100644 --- a/drivers/accel/amdxdna/aie2_ctx.c +++ b/drivers/accel/amdxdna/aie2_ctx.c @@ -468,6 +468,12 @@ static int aie2_alloc_resource(struct amdxdna_hwctx *hwctx) struct alloc_requests *xrs_req; int ret; + if (AIE2_FEATURE_ON(xdna->dev_handle, AIE2_TEMPORAL_ONLY)) { + hwctx->num_unused_col = xdna->dev_handle->total_col - hwctx->num_col; + hwctx->num_col = xdna->dev_handle->total_col; + return aie2_create_context(xdna->dev_handle, hwctx); + } + xrs_req = kzalloc(sizeof(*xrs_req), GFP_KERNEL); if (!xrs_req) return -ENOMEM; @@ -499,9 +505,15 @@ static void aie2_release_resource(struct amdxdna_hwctx *hwctx) struct amdxdna_dev *xdna = hwctx->client->xdna; int ret; - ret = xrs_release_resource(xdna->xrs_hdl, (uintptr_t)hwctx); - if (ret) - XDNA_ERR(xdna, "Release AIE resource failed, ret %d", ret); + if (AIE2_FEATURE_ON(xdna->dev_handle, AIE2_TEMPORAL_ONLY)) { + ret = aie2_destroy_context(xdna->dev_handle, hwctx); + if (ret) + XDNA_ERR(xdna, "Destroy temporal only context failed, ret %d", ret); + } else { + ret = xrs_release_resource(xdna->xrs_hdl, (uintptr_t)hwctx); + if (ret) + XDNA_ERR(xdna, "Release AIE resource failed, ret %d", ret); + } } static int aie2_ctx_syncobj_create(struct amdxdna_hwctx *hwctx) diff --git a/drivers/accel/amdxdna/aie2_message.c b/drivers/accel/amdxdna/aie2_message.c index 03b75757a6e6..051f4ceaabae 100644 --- a/drivers/accel/amdxdna/aie2_message.c +++ b/drivers/accel/amdxdna/aie2_message.c @@ -192,6 +192,40 @@ int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev, return 0; } +static int aie2_destroy_context_req(struct amdxdna_dev_hdl *ndev, u32 id) +{ + DECLARE_AIE2_MSG(destroy_ctx, MSG_OP_DESTROY_CONTEXT); + struct amdxdna_dev *xdna = ndev->xdna; + int ret; + + req.context_id = id; + ret = aie2_send_mgmt_msg_wait(ndev, &msg); + if (ret) + XDNA_WARN(xdna, "Destroy context failed, ret %d", ret); + + return ret; +} + +static u32 aie2_get_context_priority(struct amdxdna_dev_hdl *ndev, + struct amdxdna_hwctx *hwctx) +{ + if (!AIE2_FEATURE_ON(ndev, AIE2_PREEMPT)) + return PRIORITY_HIGH; + + switch (hwctx->qos.priority) { + case AMDXDNA_QOS_REALTIME_PRIORITY: + return PRIORITY_REALTIME; + case AMDXDNA_QOS_HIGH_PRIORITY: + return PRIORITY_HIGH; + case AMDXDNA_QOS_NORMAL_PRIORITY: + return PRIORITY_NORMAL; + case AMDXDNA_QOS_LOW_PRIORITY: + return PRIORITY_LOW; + default: + return PRIORITY_HIGH; + } +} + int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx) { DECLARE_AIE2_MSG(create_ctx, MSG_OP_CREATE_CONTEXT); @@ -205,22 +239,24 @@ int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwct req.aie_type = 1; req.start_col = hwctx->start_col; req.num_col = hwctx->num_col; + req.num_unused_col = hwctx->num_unused_col; req.num_cq_pairs_requested = 1; req.pasid = hwctx->client->pasid; - req.context_priority = 2; + req.context_priority = aie2_get_context_priority(ndev, hwctx); ret = aie2_send_mgmt_msg_wait(ndev, &msg); if (ret) return ret; hwctx->fw_ctx_id = resp.context_id; - WARN_ONCE(hwctx->fw_ctx_id == -1, "Unexpected context id"); + if (WARN_ON_ONCE(hwctx->fw_ctx_id == -1)) + return -EINVAL; if (ndev->force_preempt_enabled) { ret = aie2_runtime_cfg(ndev, AIE2_RT_CFG_FORCE_PREEMPT, &hwctx->fw_ctx_id); if (ret) { XDNA_ERR(xdna, "failed to enable force preempt %d", ret); - return ret; + goto del_ctx_req; } } @@ -237,51 +273,39 @@ int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwct ret = pci_irq_vector(to_pci_dev(xdna->ddev.dev), resp.msix_id); if (ret == -EINVAL) { - XDNA_ERR(xdna, "not able to create channel"); - goto out_destroy_context; + XDNA_ERR(xdna, "Alloc IRQ failed %d", ret); + goto del_ctx_req; } intr_reg = i2x.mb_head_ptr_reg + 4; hwctx->priv->mbox_chann = xdna_mailbox_create_channel(ndev->mbox, &x2i, &i2x, intr_reg, ret); if (!hwctx->priv->mbox_chann) { - XDNA_ERR(xdna, "not able to create channel"); + XDNA_ERR(xdna, "Not able to create channel"); ret = -EINVAL; - goto out_destroy_context; + goto del_ctx_req; } ndev->hwctx_num++; - XDNA_DBG(xdna, "%s mailbox channel irq: %d, msix_id: %d", - hwctx->name, ret, resp.msix_id); - XDNA_DBG(xdna, "%s created fw ctx %d pasid %d", hwctx->name, - hwctx->fw_ctx_id, hwctx->client->pasid); + XDNA_DBG(xdna, "Mailbox channel irq: %d, msix_id: %d", ret, resp.msix_id); + XDNA_DBG(xdna, "Created fw ctx %d pasid %d", hwctx->fw_ctx_id, hwctx->client->pasid); return 0; -out_destroy_context: - aie2_destroy_context(ndev, hwctx); +del_ctx_req: + aie2_destroy_context_req(ndev, hwctx->fw_ctx_id); return ret; } int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx) { - DECLARE_AIE2_MSG(destroy_ctx, MSG_OP_DESTROY_CONTEXT); struct amdxdna_dev *xdna = ndev->xdna; int ret; - if (hwctx->fw_ctx_id == -1) - return 0; - xdna_mailbox_stop_channel(hwctx->priv->mbox_chann); - - req.context_id = hwctx->fw_ctx_id; - ret = aie2_send_mgmt_msg_wait(ndev, &msg); - if (ret) - XDNA_WARN(xdna, "%s destroy context failed, ret %d", hwctx->name, ret); - + ret = aie2_destroy_context_req(ndev, hwctx->fw_ctx_id); xdna_mailbox_destroy_channel(hwctx->priv->mbox_chann); - XDNA_DBG(xdna, "%s destroyed fw ctx %d", hwctx->name, - hwctx->fw_ctx_id); + XDNA_DBG(xdna, "Destroyed fw ctx %d", hwctx->fw_ctx_id); hwctx->priv->mbox_chann = NULL; hwctx->fw_ctx_id = -1; ndev->hwctx_num--; diff --git a/drivers/accel/amdxdna/aie2_msg_priv.h b/drivers/accel/amdxdna/aie2_msg_priv.h index 1c957a6298d3..728ef56f7f0a 100644 --- a/drivers/accel/amdxdna/aie2_msg_priv.h +++ b/drivers/accel/amdxdna/aie2_msg_priv.h @@ -108,11 +108,17 @@ struct cq_pair { struct cq_info i2x_q; }; +#define PRIORITY_REALTIME 1 +#define PRIORITY_HIGH 2 +#define PRIORITY_NORMAL 3 +#define PRIORITY_LOW 4 + struct create_ctx_req { __u32 aie_type; __u8 start_col; __u8 num_col; - __u16 reserved; + __u8 num_unused_col; + __u8 reserved; __u8 num_cq_pairs_requested; __u8 reserved1; __u16 pasid; diff --git a/drivers/accel/amdxdna/aie2_pci.h b/drivers/accel/amdxdna/aie2_pci.h index c6b5cf4ae5c4..a929fa98a121 100644 --- a/drivers/accel/amdxdna/aie2_pci.h +++ b/drivers/accel/amdxdna/aie2_pci.h @@ -232,6 +232,7 @@ struct aie2_hw_ops { enum aie2_fw_feature { AIE2_NPU_COMMAND, AIE2_PREEMPT, + AIE2_TEMPORAL_ONLY, AIE2_FEATURE_MAX }; diff --git a/drivers/accel/amdxdna/amdxdna_ctx.h b/drivers/accel/amdxdna/amdxdna_ctx.h index b6151244d64f..b29449a92f60 100644 --- a/drivers/accel/amdxdna/amdxdna_ctx.h +++ b/drivers/accel/amdxdna/amdxdna_ctx.h @@ -98,6 +98,7 @@ struct amdxdna_hwctx { u32 *col_list; u32 start_col; u32 num_col; + u32 num_unused_col; #define HWCTX_STAT_INIT 0 #define HWCTX_STAT_READY 1 #define HWCTX_STAT_STOP 2 diff --git a/drivers/accel/amdxdna/amdxdna_mailbox.c b/drivers/accel/amdxdna/amdxdna_mailbox.c index a60a85ce564c..469242ed8224 100644 --- a/drivers/accel/amdxdna/amdxdna_mailbox.c +++ b/drivers/accel/amdxdna/amdxdna_mailbox.c @@ -191,26 +191,34 @@ mailbox_send_msg(struct mailbox_channel *mb_chann, struct mailbox_msg *mb_msg) u32 head, tail; u32 start_addr; u32 tmp_tail; + int ret; head = mailbox_get_headptr(mb_chann, CHAN_RES_X2I); tail = mb_chann->x2i_tail; - ringbuf_size = mailbox_get_ringbuf_size(mb_chann, CHAN_RES_X2I); + ringbuf_size = mailbox_get_ringbuf_size(mb_chann, CHAN_RES_X2I) - sizeof(u32); start_addr = mb_chann->res[CHAN_RES_X2I].rb_start_addr; tmp_tail = tail + mb_msg->pkg_size; - if (tail < head && tmp_tail >= head) - goto no_space; - if (tail >= head && (tmp_tail > ringbuf_size - sizeof(u32) && - mb_msg->pkg_size >= head)) - goto no_space; - - if (tail >= head && tmp_tail > ringbuf_size - sizeof(u32)) { +check_again: + if (tail >= head && tmp_tail > ringbuf_size) { write_addr = mb_chann->mb->res.ringbuf_base + start_addr + tail; writel(TOMBSTONE, write_addr); /* tombstone is set. Write from the start of the ringbuf */ tail = 0; + tmp_tail = tail + mb_msg->pkg_size; + } + + if (tail < head && tmp_tail >= head) { + ret = read_poll_timeout(mailbox_get_headptr, head, + tmp_tail < head || tail >= head, + 1, 100, false, mb_chann, CHAN_RES_X2I); + if (ret) + return ret; + + if (tail >= head) + goto check_again; } write_addr = mb_chann->mb->res.ringbuf_base + start_addr + tail; @@ -222,9 +230,6 @@ mailbox_send_msg(struct mailbox_channel *mb_chann, struct mailbox_msg *mb_msg) mb_msg->pkg.header.id); return 0; - -no_space: - return -ENOSPC; } static int diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c b/drivers/accel/amdxdna/amdxdna_pci_drv.c index 1973ab67721b..7d59764d7869 100644 --- a/drivers/accel/amdxdna/amdxdna_pci_drv.c +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c @@ -51,7 +51,6 @@ MODULE_DEVICE_TABLE(pci, pci_ids); static const struct amdxdna_device_id amdxdna_ids[] = { { 0x1502, 0x0, &dev_npu1_info }, - { 0x17f0, 0x0, &dev_npu2_info }, { 0x17f0, 0x10, &dev_npu4_info }, { 0x17f0, 0x11, &dev_npu5_info }, { 0x17f0, 0x20, &dev_npu6_info }, @@ -105,43 +104,38 @@ static int amdxdna_drm_open(struct drm_device *ddev, struct drm_file *filp) return ret; } -static void amdxdna_drm_close(struct drm_device *ddev, struct drm_file *filp) +static void amdxdna_client_cleanup(struct amdxdna_client *client) { - struct amdxdna_client *client = filp->driver_priv; - struct amdxdna_dev *xdna = to_xdna_dev(ddev); - - XDNA_DBG(xdna, "closing pid %d", client->pid); - + list_del(&client->node); + amdxdna_hwctx_remove_all(client); xa_destroy(&client->hwctx_xa); cleanup_srcu_struct(&client->hwctx_srcu); mutex_destroy(&client->mm_lock); + if (client->dev_heap) drm_gem_object_put(to_gobj(client->dev_heap)); iommu_sva_unbind_device(client->sva); - XDNA_DBG(xdna, "pid %d closed", client->pid); kfree(client); } -static int amdxdna_flush(struct file *f, fl_owner_t id) +static void amdxdna_drm_close(struct drm_device *ddev, struct drm_file *filp) { - struct drm_file *filp = f->private_data; struct amdxdna_client *client = filp->driver_priv; - struct amdxdna_dev *xdna = client->xdna; + struct amdxdna_dev *xdna = to_xdna_dev(ddev); int idx; - XDNA_DBG(xdna, "PID %d flushing...", client->pid); + XDNA_DBG(xdna, "closing pid %d", client->pid); + if (!drm_dev_enter(&xdna->ddev, &idx)) - return 0; + return; mutex_lock(&xdna->dev_lock); - list_del_init(&client->node); - amdxdna_hwctx_remove_all(client); + amdxdna_client_cleanup(client); mutex_unlock(&xdna->dev_lock); drm_dev_exit(idx); - return 0; } static int amdxdna_drm_get_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) @@ -217,7 +211,6 @@ static const struct file_operations amdxdna_fops = { .owner = THIS_MODULE, .open = accel_open, .release = drm_release, - .flush = amdxdna_flush, .unlocked_ioctl = drm_ioctl, .compat_ioctl = drm_compat_ioctl, .poll = drm_poll, @@ -333,8 +326,7 @@ static void amdxdna_remove(struct pci_dev *pdev) client = list_first_entry_or_null(&xdna->client_list, struct amdxdna_client, node); while (client) { - list_del_init(&client->node); - amdxdna_hwctx_remove_all(client); + amdxdna_client_cleanup(client); client = list_first_entry_or_null(&xdna->client_list, struct amdxdna_client, node); diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h index 0d50c4c8b353..6580cb5ec7e2 100644 --- a/drivers/accel/amdxdna/amdxdna_pci_drv.h +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h @@ -137,7 +137,6 @@ struct amdxdna_client { /* Add device info below */ extern const struct amdxdna_dev_info dev_npu1_info; -extern const struct amdxdna_dev_info dev_npu2_info; extern const struct amdxdna_dev_info dev_npu4_info; extern const struct amdxdna_dev_info dev_npu5_info; extern const struct amdxdna_dev_info dev_npu6_info; diff --git a/drivers/accel/amdxdna/npu2_regs.c b/drivers/accel/amdxdna/npu2_regs.c deleted file mode 100644 index ad0743fb06d5..000000000000 --- a/drivers/accel/amdxdna/npu2_regs.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023-2024, Advanced Micro Devices, Inc. - */ - -#include -#include -#include -#include - -#include "aie2_pci.h" -#include "amdxdna_mailbox.h" -#include "amdxdna_pci_drv.h" - -/* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */ -#define MPNPU_PWAITMODE 0x301003C -#define MPNPU_PUB_SEC_INTR 0x3010060 -#define MPNPU_PUB_PWRMGMT_INTR 0x3010064 -#define MPNPU_PUB_SCRATCH0 0x301006C -#define MPNPU_PUB_SCRATCH1 0x3010070 -#define MPNPU_PUB_SCRATCH2 0x3010074 -#define MPNPU_PUB_SCRATCH3 0x3010078 -#define MPNPU_PUB_SCRATCH4 0x301007C -#define MPNPU_PUB_SCRATCH5 0x3010080 -#define MPNPU_PUB_SCRATCH6 0x3010084 -#define MPNPU_PUB_SCRATCH7 0x3010088 -#define MPNPU_PUB_SCRATCH8 0x301008C -#define MPNPU_PUB_SCRATCH9 0x3010090 -#define MPNPU_PUB_SCRATCH10 0x3010094 -#define MPNPU_PUB_SCRATCH11 0x3010098 -#define MPNPU_PUB_SCRATCH12 0x301009C -#define MPNPU_PUB_SCRATCH13 0x30100A0 -#define MPNPU_PUB_SCRATCH14 0x30100A4 -#define MPNPU_PUB_SCRATCH15 0x30100A8 -#define MP0_C2PMSG_73 0x3810A24 -#define MP0_C2PMSG_123 0x3810AEC - -#define MP1_C2PMSG_0 0x3B10900 -#define MP1_C2PMSG_60 0x3B109F0 -#define MP1_C2PMSG_61 0x3B109F4 - -#define MPNPU_SRAM_X2I_MAILBOX_0 0x3600000 -#define MPNPU_SRAM_X2I_MAILBOX_15 0x361E000 -#define MPNPU_SRAM_X2I_MAILBOX_31 0x363E000 -#define MPNPU_SRAM_I2X_MAILBOX_31 0x363F000 - -#define MMNPU_APERTURE0_BASE 0x3000000 -#define MMNPU_APERTURE1_BASE 0x3600000 -#define MMNPU_APERTURE3_BASE 0x3810000 -#define MMNPU_APERTURE4_BASE 0x3B10000 - -/* PCIe BAR Index for NPU2 */ -#define NPU2_REG_BAR_INDEX 0 -#define NPU2_MBOX_BAR_INDEX 0 -#define NPU2_PSP_BAR_INDEX 4 -#define NPU2_SMU_BAR_INDEX 5 -#define NPU2_SRAM_BAR_INDEX 2 -/* Associated BARs and Apertures */ -#define NPU2_REG_BAR_BASE MMNPU_APERTURE0_BASE -#define NPU2_MBOX_BAR_BASE MMNPU_APERTURE0_BASE -#define NPU2_PSP_BAR_BASE MMNPU_APERTURE3_BASE -#define NPU2_SMU_BAR_BASE MMNPU_APERTURE4_BASE -#define NPU2_SRAM_BAR_BASE MMNPU_APERTURE1_BASE - -static const struct amdxdna_dev_priv npu2_dev_priv = { - .fw_path = "amdnpu/17f0_00/npu.sbin", - .protocol_major = 0x6, - .protocol_minor = 0x6, - .rt_config = npu4_default_rt_cfg, - .dpm_clk_tbl = npu4_dpm_clk_table, - .fw_feature_tbl = npu4_fw_feature_table, - .col_align = COL_ALIGN_NATURE, - .mbox_dev_addr = NPU2_MBOX_BAR_BASE, - .mbox_size = 0, /* Use BAR size */ - .sram_dev_addr = NPU2_SRAM_BAR_BASE, - .hwctx_limit = 16, - .sram_offs = { - DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU2_SRAM, MPNPU_SRAM_X2I_MAILBOX_0), - DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU2_SRAM, MPNPU_SRAM_X2I_MAILBOX_15), - }, - .psp_regs_off = { - DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU2_PSP, MP0_C2PMSG_123), - DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU2_REG, MPNPU_PUB_SCRATCH3), - DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU2_REG, MPNPU_PUB_SCRATCH4), - DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU2_REG, MPNPU_PUB_SCRATCH9), - DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU2_PSP, MP0_C2PMSG_73), - DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU2_PSP, MP0_C2PMSG_123), - DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU2_REG, MPNPU_PUB_SCRATCH3), - DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU2_REG, MPNPU_PWAITMODE), - }, - .smu_regs_off = { - DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU2_SMU, MP1_C2PMSG_0), - DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU2_SMU, MP1_C2PMSG_60), - DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU2_SMU, MMNPU_APERTURE4_BASE), - DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU2_SMU, MP1_C2PMSG_61), - DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU2_SMU, MP1_C2PMSG_60), - }, - .hw_ops = { - .set_dpm = npu4_set_dpm, - }, -}; - -const struct amdxdna_dev_info dev_npu2_info = { - .reg_bar = NPU2_REG_BAR_INDEX, - .mbox_bar = NPU2_MBOX_BAR_INDEX, - .sram_bar = NPU2_SRAM_BAR_INDEX, - .psp_bar = NPU2_PSP_BAR_INDEX, - .smu_bar = NPU2_SMU_BAR_INDEX, - .first_col = 0, - .dev_mem_buf_shift = 15, /* 32 KiB aligned */ - .dev_mem_base = AIE2_DEVM_BASE, - .dev_mem_size = AIE2_DEVM_SIZE, - .vbnv = "RyzenAI-npu2", - .device_type = AMDXDNA_DEV_TYPE_KMQ, - .dev_priv = &npu2_dev_priv, - .ops = &aie2_ops, /* NPU2 can share NPU1's callback */ -}; diff --git a/drivers/accel/amdxdna/npu4_regs.c b/drivers/accel/amdxdna/npu4_regs.c index 4ca21db70478..a62234fd266d 100644 --- a/drivers/accel/amdxdna/npu4_regs.c +++ b/drivers/accel/amdxdna/npu4_regs.c @@ -90,6 +90,7 @@ const struct dpm_clk_freq npu4_dpm_clk_table[] = { const struct aie2_fw_feature_tbl npu4_fw_feature_table[] = { { .feature = AIE2_NPU_COMMAND, .min_minor = 15 }, { .feature = AIE2_PREEMPT, .min_minor = 12 }, + { .feature = AIE2_TEMPORAL_ONLY, .min_minor = 12 }, { 0 } }; diff --git a/drivers/accel/ivpu/ivpu_gem.c b/drivers/accel/ivpu/ivpu_gem.c index ece68f570b7e..98b9ce26962b 100644 --- a/drivers/accel/ivpu/ivpu_gem.c +++ b/drivers/accel/ivpu/ivpu_gem.c @@ -95,7 +95,7 @@ int __must_check ivpu_bo_bind(struct ivpu_bo *bo) if (!bo->mmu_mapped) { drm_WARN_ON(&vdev->drm, !bo->ctx); - ret = ivpu_mmu_context_map_sgt(vdev, bo->ctx, bo->vpu_addr, sgt, + ret = ivpu_mmu_context_map_sgt(vdev, bo->ctx, bo->vpu_addr, sgt, ivpu_bo_size(bo), ivpu_bo_is_snooped(bo), ivpu_bo_is_read_only(bo)); if (ret) { ivpu_err(vdev, "Failed to map BO in MMU: %d\n", ret); diff --git a/drivers/accel/ivpu/ivpu_mmu_context.c b/drivers/accel/ivpu/ivpu_mmu_context.c index 87ad593ef47d..c4014c83e727 100644 --- a/drivers/accel/ivpu/ivpu_mmu_context.c +++ b/drivers/accel/ivpu/ivpu_mmu_context.c @@ -429,11 +429,12 @@ static void ivpu_mmu_context_unmap_pages(struct ivpu_mmu_context *ctx, u64 vpu_a } int -ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, - u64 vpu_addr, struct sg_table *sgt, bool llc_coherent, bool read_only) +ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u64 vpu_addr, + struct sg_table *sgt, size_t bo_size, bool llc_coherent, bool read_only) { size_t start_vpu_addr = vpu_addr; struct scatterlist *sg; + size_t sgt_size = 0; int ret; u64 prot; u64 i; @@ -462,12 +463,25 @@ ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, ivpu_dbg(vdev, MMU_MAP, "Map ctx: %u dma_addr: 0x%llx vpu_addr: 0x%llx size: %lu\n", ctx->id, dma_addr, vpu_addr, size); + if (sgt_size + size > bo_size) { + ivpu_err(vdev, "Scatter-gather table size exceeds buffer object size\n"); + ret = -EINVAL; + goto err_unmap_pages; + } + ret = ivpu_mmu_context_map_pages(vdev, ctx, vpu_addr, dma_addr, size, prot); if (ret) { ivpu_err(vdev, "Failed to map context pages\n"); goto err_unmap_pages; } vpu_addr += size; + sgt_size += size; + } + + if (sgt_size < bo_size) { + ivpu_err(vdev, "Scatter-gather table size too small to cover buffer object size\n"); + ret = -EINVAL; + goto err_unmap_pages; } if (!ctx->is_cd_valid) { @@ -493,7 +507,7 @@ ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, return 0; err_unmap_pages: - ivpu_mmu_context_unmap_pages(ctx, start_vpu_addr, vpu_addr - start_vpu_addr); + ivpu_mmu_context_unmap_pages(ctx, start_vpu_addr, sgt_size); mutex_unlock(&ctx->lock); return ret; } diff --git a/drivers/accel/ivpu/ivpu_mmu_context.h b/drivers/accel/ivpu/ivpu_mmu_context.h index 663a11a9db11..cc02e7bab04e 100644 --- a/drivers/accel/ivpu/ivpu_mmu_context.h +++ b/drivers/accel/ivpu/ivpu_mmu_context.h @@ -41,8 +41,9 @@ int ivpu_mmu_context_insert_node(struct ivpu_mmu_context *ctx, const struct ivpu u64 size, struct drm_mm_node *node); void ivpu_mmu_context_remove_node(struct ivpu_mmu_context *ctx, struct drm_mm_node *node); -int ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, - u64 vpu_addr, struct sg_table *sgt, bool llc_coherent, bool read_only); +int +ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u64 vpu_addr, + struct sg_table *sgt, size_t bo_size, bool llc_coherent, bool read_only); void ivpu_mmu_context_unmap_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u64 vpu_addr, struct sg_table *sgt); int ivpu_mmu_context_set_pages_ro(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index 4a7716a5b7c6..a4d8f2ff94e4 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -35,6 +35,28 @@ #include "dma-buf-sysfs-stats.h" +#define CREATE_TRACE_POINTS +#include + +/* + * dmabuf->name must be accessed with holding dmabuf->name_lock. + * we need to take the lock around the tracepoint call itself where + * it is called in the code. + * + * Note: FUNC##_enabled() is a static branch that will only + * be set when the trace event is enabled. + */ +#define DMA_BUF_TRACE(FUNC, ...) \ + do { \ + if (FUNC##_enabled()) { \ + guard(spinlock)(&dmabuf->name_lock); \ + FUNC(__VA_ARGS__); \ + } else if (IS_ENABLED(CONFIG_LOCKDEP)) { \ + /* Expose this lock when lockdep is enabled */ \ + guard(spinlock)(&dmabuf->name_lock); \ + } \ + } while (0) + /* Wrapper to hide the sg_table page link from the importer */ struct dma_buf_sg_table_wrapper { struct sg_table *original; @@ -226,6 +248,8 @@ static int dma_buf_mmap_internal(struct file *file, struct vm_area_struct *vma) dmabuf->size >> PAGE_SHIFT) return -EINVAL; + DMA_BUF_TRACE(trace_dma_buf_mmap_internal, dmabuf); + return dmabuf->ops->mmap(dmabuf, vma); } @@ -751,6 +775,8 @@ struct dma_buf *dma_buf_export(const struct dma_buf_export_info *exp_info) __dma_buf_list_add(dmabuf); + DMA_BUF_TRACE(trace_dma_buf_export, dmabuf); + return dmabuf; err_dmabuf: @@ -774,10 +800,16 @@ EXPORT_SYMBOL_NS_GPL(dma_buf_export, "DMA_BUF"); */ int dma_buf_fd(struct dma_buf *dmabuf, int flags) { + int fd; + if (!dmabuf || !dmabuf->file) return -EINVAL; - return FD_ADD(flags, dmabuf->file); + fd = FD_ADD(flags, dmabuf->file); + if (fd >= 0) + DMA_BUF_TRACE(trace_dma_buf_fd, dmabuf, fd); + + return fd; } EXPORT_SYMBOL_NS_GPL(dma_buf_fd, "DMA_BUF"); @@ -792,6 +824,7 @@ EXPORT_SYMBOL_NS_GPL(dma_buf_fd, "DMA_BUF"); struct dma_buf *dma_buf_get(int fd) { struct file *file; + struct dma_buf *dmabuf; file = fget(fd); @@ -803,7 +836,11 @@ struct dma_buf *dma_buf_get(int fd) return ERR_PTR(-EINVAL); } - return file->private_data; + dmabuf = file->private_data; + + DMA_BUF_TRACE(trace_dma_buf_get, dmabuf, fd); + + return dmabuf; } EXPORT_SYMBOL_NS_GPL(dma_buf_get, "DMA_BUF"); @@ -823,6 +860,8 @@ void dma_buf_put(struct dma_buf *dmabuf) return; fput(dmabuf->file); + + DMA_BUF_TRACE(trace_dma_buf_put, dmabuf); } EXPORT_SYMBOL_NS_GPL(dma_buf_put, "DMA_BUF"); @@ -1015,6 +1054,9 @@ dma_buf_dynamic_attach(struct dma_buf *dmabuf, struct device *dev, list_add(&attach->node, &dmabuf->attachments); dma_resv_unlock(dmabuf->resv); + DMA_BUF_TRACE(trace_dma_buf_dynamic_attach, dmabuf, attach, + dma_buf_attachment_is_dynamic(attach), dev); + return attach; err_attach: @@ -1059,6 +1101,9 @@ void dma_buf_detach(struct dma_buf *dmabuf, struct dma_buf_attachment *attach) if (dmabuf->ops->detach) dmabuf->ops->detach(dmabuf, attach); + DMA_BUF_TRACE(trace_dma_buf_detach, dmabuf, attach, + dma_buf_attachment_is_dynamic(attach), attach->dev); + kfree(attach); } EXPORT_SYMBOL_NS_GPL(dma_buf_detach, "DMA_BUF"); @@ -1525,6 +1570,8 @@ int dma_buf_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma, vma_set_file(vma, dmabuf->file); vma->vm_pgoff = pgoff; + DMA_BUF_TRACE(trace_dma_buf_mmap, dmabuf); + return dmabuf->ops->mmap(dmabuf, vma); } EXPORT_SYMBOL_NS_GPL(dma_buf_mmap, "DMA_BUF"); diff --git a/drivers/dma-buf/st-dma-fence.c b/drivers/dma-buf/st-dma-fence.c index 4dbe39c58bfb..73ed6fd48a13 100644 --- a/drivers/dma-buf/st-dma-fence.c +++ b/drivers/dma-buf/st-dma-fence.c @@ -33,50 +33,9 @@ static void mock_fence_release(struct dma_fence *f) kmem_cache_free(slab_fences, to_mock_fence(f)); } -struct wait_cb { - struct dma_fence_cb cb; - struct task_struct *task; -}; - -static void mock_wakeup(struct dma_fence *f, struct dma_fence_cb *cb) -{ - wake_up_process(container_of(cb, struct wait_cb, cb)->task); -} - -static long mock_wait(struct dma_fence *f, bool intr, long timeout) -{ - const int state = intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; - struct wait_cb cb = { .task = current }; - - if (dma_fence_add_callback(f, &cb.cb, mock_wakeup)) - return timeout; - - while (timeout) { - set_current_state(state); - - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &f->flags)) - break; - - if (signal_pending_state(state, current)) - break; - - timeout = schedule_timeout(timeout); - } - __set_current_state(TASK_RUNNING); - - if (!dma_fence_remove_callback(f, &cb.cb)) - return timeout; - - if (signal_pending_state(state, current)) - return -ERESTARTSYS; - - return -ETIME; -} - static const struct dma_fence_ops mock_ops = { .get_driver_name = mock_name, .get_timeline_name = mock_name, - .wait = mock_wait, .release = mock_fence_release, }; @@ -349,14 +308,14 @@ static int test_wait(void *arg) dma_fence_enable_sw_signaling(f); - if (dma_fence_wait_timeout(f, false, 0) != -ETIME) { + if (dma_fence_wait_timeout(f, false, 0) != 0) { pr_err("Wait reported complete before being signaled\n"); goto err_free; } dma_fence_signal(f); - if (dma_fence_wait_timeout(f, false, 0) != 0) { + if (dma_fence_wait_timeout(f, false, 0) != 1) { pr_err("Wait reported incomplete after being signaled\n"); goto err_free; } @@ -393,16 +352,16 @@ static int test_wait_timeout(void *arg) dma_fence_enable_sw_signaling(wt.f); - if (dma_fence_wait_timeout(wt.f, false, 1) != -ETIME) { + if (dma_fence_wait_timeout(wt.f, false, 1) != 0) { pr_err("Wait reported complete before being signaled\n"); goto err_free; } mod_timer(&wt.timer, jiffies + 1); - if (dma_fence_wait_timeout(wt.f, false, 2) == -ETIME) { + if (dma_fence_wait_timeout(wt.f, false, HZ) == 0) { if (timer_pending(&wt.timer)) { - pr_notice("Timer did not fire within the jiffy!\n"); + pr_notice("Timer did not fire within one HZ!\n"); err = 0; /* not our fault! */ } else { pr_err("Wait reported incomplete after timeout\n"); diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c index 29174ab58ff3..fbd1164174b0 100644 --- a/drivers/gpu/drm/drm_gem_shmem_helper.c +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c @@ -94,9 +94,12 @@ static int __drm_gem_shmem_init(struct drm_device *dev, struct drm_gem_shmem_obj } /** - * drm_gem_shmem_init - Initialize an allocated object. + * drm_gem_shmem_init - Initialize an allocated object of the given size * @dev: DRM device - * @obj: The allocated shmem GEM object. + * @shmem: shmem GEM object to initialize + * @size: Size of the object to initialize + * + * This function initializes an allocated shmem GEM object. * * Returns: * 0 on success, or a negative error code on failure. diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c index e1b0fa4000cd..2d4ab745fdad 100644 --- a/drivers/gpu/drm/drm_syncobj.c +++ b/drivers/gpu/drm/drm_syncobj.c @@ -250,14 +250,14 @@ struct drm_syncobj *drm_syncobj_find(struct drm_file *file_private, { struct drm_syncobj *syncobj; - spin_lock(&file_private->syncobj_table_lock); + xa_lock(&file_private->syncobj_xa); /* Check if we currently have a reference on the object */ - syncobj = idr_find(&file_private->syncobj_idr, handle); + syncobj = xa_load(&file_private->syncobj_xa, handle); if (syncobj) drm_syncobj_get(syncobj); - spin_unlock(&file_private->syncobj_table_lock); + xa_unlock(&file_private->syncobj_xa); return syncobj; } @@ -598,23 +598,15 @@ int drm_syncobj_get_handle(struct drm_file *file_private, { int ret; - /* take a reference to put in the idr */ + /* take a reference to put in the xarray */ drm_syncobj_get(syncobj); - idr_preload(GFP_KERNEL); - spin_lock(&file_private->syncobj_table_lock); - ret = idr_alloc(&file_private->syncobj_idr, syncobj, 1, 0, GFP_NOWAIT); - spin_unlock(&file_private->syncobj_table_lock); - - idr_preload_end(); - - if (ret < 0) { + ret = xa_alloc(&file_private->syncobj_xa, handle, syncobj, xa_limit_32b, + GFP_NOWAIT); + if (ret) drm_syncobj_put(syncobj); - return ret; - } - *handle = ret; - return 0; + return ret; } EXPORT_SYMBOL(drm_syncobj_get_handle); @@ -638,10 +630,7 @@ static int drm_syncobj_destroy(struct drm_file *file_private, { struct drm_syncobj *syncobj; - spin_lock(&file_private->syncobj_table_lock); - syncobj = idr_remove(&file_private->syncobj_idr, handle); - spin_unlock(&file_private->syncobj_table_lock); - + syncobj = xa_erase(&file_private->syncobj_xa, handle); if (!syncobj) return -EINVAL; @@ -722,20 +711,13 @@ static int drm_syncobj_fd_to_handle(struct drm_file *file_private, if (fd_file(f)->f_op != &drm_syncobj_file_fops) return -EINVAL; - /* take a reference to put in the idr */ + /* take a reference to put in the xarray */ syncobj = fd_file(f)->private_data; drm_syncobj_get(syncobj); - idr_preload(GFP_KERNEL); - spin_lock(&file_private->syncobj_table_lock); - ret = idr_alloc(&file_private->syncobj_idr, syncobj, 1, 0, GFP_NOWAIT); - spin_unlock(&file_private->syncobj_table_lock); - idr_preload_end(); - - if (ret > 0) { - *handle = ret; - ret = 0; - } else + ret = xa_alloc(&file_private->syncobj_xa, handle, syncobj, xa_limit_32b, + GFP_NOWAIT); + if (ret) drm_syncobj_put(syncobj); return ret; @@ -814,17 +796,7 @@ static int drm_syncobj_export_sync_file(struct drm_file *file_private, void drm_syncobj_open(struct drm_file *file_private) { - idr_init_base(&file_private->syncobj_idr, 1); - spin_lock_init(&file_private->syncobj_table_lock); -} - -static int -drm_syncobj_release_handle(int id, void *ptr, void *data) -{ - struct drm_syncobj *syncobj = ptr; - - drm_syncobj_put(syncobj); - return 0; + xa_init_flags(&file_private->syncobj_xa, XA_FLAGS_ALLOC1); } /** @@ -838,9 +810,12 @@ drm_syncobj_release_handle(int id, void *ptr, void *data) void drm_syncobj_release(struct drm_file *file_private) { - idr_for_each(&file_private->syncobj_idr, - &drm_syncobj_release_handle, file_private); - idr_destroy(&file_private->syncobj_idr); + struct drm_syncobj *syncobj; + unsigned long handle; + + xa_for_each(&file_private->syncobj_xa, handle, syncobj) + drm_syncobj_put(syncobj); + xa_destroy(&file_private->syncobj_xa); } int diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 7a83804fedca..307152ad7759 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -781,6 +781,19 @@ config DRM_PANEL_SAMSUNG_LD9040 depends on BACKLIGHT_CLASS_DEVICE select VIDEOMODE_HELPERS +config DRM_PANEL_SAMSUNG_LTL106HL02 + tristate "Samsung LTL106HL02 panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + select VIDEOMODE_HELPERS + help + Say Y here if you want to enable support for the Samsung LTL106HL02 + panel driver which is used in Microsoft Surface 2. + + To compile this driver as a module, choose M here: the module + will be called panel-samsung-ltl106hl02. + config DRM_PANEL_SAMSUNG_S6E3FA7 tristate "Samsung S6E3FA7 panel driver" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index b9562a6fdcb3..aeffaa95666d 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08) += panel-samsung-ams639rq08.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20) += panel-samsung-atna33xc20.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_DB7430) += panel-samsung-db7430.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o +obj-$(CONFIG_DRM_PANEL_SAMSUNG_LTL106HL02) += panel-samsung-ltl106hl02.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D16D0) += panel-samsung-s6d16d0.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D27A1) += panel-samsung-s6d27a1.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0) += panel-samsung-s6d7aa0.o diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/panel/panel-lg-sw43408.c index 46a56ea92ad9..293826c5006b 100644 --- a/drivers/gpu/drm/panel/panel-lg-sw43408.c +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -20,13 +20,18 @@ #include #include -#define NUM_SUPPLIES 2 +static const struct regulator_bulk_data sw43408_supplies[] = { + { .supply = "vddi", /* 1.8 V */ + .init_load_uA = 62000 }, + { .supply = "vpnl", /* 3.0 V */ + .init_load_uA = 857000 }, +}; struct sw43408_panel { struct drm_panel base; struct mipi_dsi_device *link; - struct regulator_bulk_data supplies[NUM_SUPPLIES]; + struct regulator_bulk_data *supplies; struct gpio_desc *reset_gpio; @@ -52,7 +57,7 @@ static int sw43408_unprepare(struct drm_panel *panel) gpiod_set_value(sw43408->reset_gpio, 1); - ret = regulator_bulk_disable(ARRAY_SIZE(sw43408->supplies), sw43408->supplies); + ret = regulator_bulk_disable(ARRAY_SIZE(sw43408_supplies), sw43408->supplies); return ret ? : ctx.accum_err; } @@ -119,23 +124,28 @@ static int sw43408_program(struct drm_panel *panel) return ctx.accum_err; } -static int sw43408_prepare(struct drm_panel *panel) +static void sw43408_reset(struct sw43408_panel *ctx) { - struct sw43408_panel *ctx = to_panel_info(panel); - int ret; - - ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); - if (ret < 0) - return ret; - - usleep_range(5000, 6000); - gpiod_set_value(ctx->reset_gpio, 0); usleep_range(9000, 10000); gpiod_set_value(ctx->reset_gpio, 1); usleep_range(1000, 2000); gpiod_set_value(ctx->reset_gpio, 0); usleep_range(9000, 10000); +} + +static int sw43408_prepare(struct drm_panel *panel) +{ + struct sw43408_panel *ctx = to_panel_info(panel); + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(sw43408_supplies), ctx->supplies); + if (ret < 0) + return ret; + + usleep_range(5000, 6000); + + sw43408_reset(ctx); ret = sw43408_program(panel); if (ret) @@ -145,11 +155,11 @@ static int sw43408_prepare(struct drm_panel *panel) poweroff: gpiod_set_value(ctx->reset_gpio, 1); - regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + regulator_bulk_disable(ARRAY_SIZE(sw43408_supplies), ctx->supplies); return ret; } -static const struct drm_display_mode sw43408_mode = { +static const struct drm_display_mode lh546wf1_ed01_mode = { .clock = (1080 + 20 + 32 + 20) * (2160 + 20 + 4 + 20) * 60 / 1000, .hdisplay = 1080, @@ -171,7 +181,7 @@ static const struct drm_display_mode sw43408_mode = { static int sw43408_get_modes(struct drm_panel *panel, struct drm_connector *connector) { - return drm_connector_helper_get_modes_fixed(connector, &sw43408_mode); + return drm_connector_helper_get_modes_fixed(connector, &lh546wf1_ed01_mode); } static int sw43408_backlight_update_status(struct backlight_device *bl) @@ -214,7 +224,8 @@ static const struct drm_panel_funcs sw43408_funcs = { }; static const struct of_device_id sw43408_of_match[] = { - { .compatible = "lg,sw43408", }, + { .compatible = "lg,sw43408", }, /* legacy */ + { .compatible = "lg,sw43408-lh546wf1-ed01", }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sw43408_of_match); @@ -224,20 +235,17 @@ static int sw43408_add(struct sw43408_panel *ctx) struct device *dev = &ctx->link->dev; int ret; - ctx->supplies[0].supply = "vddi"; /* 1.88 V */ - ctx->supplies[0].init_load_uA = 62000; - ctx->supplies[1].supply = "vpnl"; /* 3.0 V */ - ctx->supplies[1].init_load_uA = 857000; - - ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies), - ctx->supplies); + ret = devm_regulator_bulk_get_const(dev, + ARRAY_SIZE(sw43408_supplies), + sw43408_supplies, + &ctx->supplies); if (ret < 0) return ret; ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(ctx->reset_gpio)) { - ret = PTR_ERR(ctx->reset_gpio); - return dev_err_probe(dev, ret, "cannot get reset gpio\n"); + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), + "Failed to get reset-gpios\n"); } ret = sw43408_backlight_init(ctx); @@ -294,10 +302,6 @@ static void sw43408_remove(struct mipi_dsi_device *dsi) struct sw43408_panel *ctx = mipi_dsi_get_drvdata(dsi); int ret; - ret = sw43408_unprepare(&ctx->base); - if (ret < 0) - dev_err(&dsi->dev, "failed to unprepare panel: %d\n", ret); - ret = mipi_dsi_detach(dsi); if (ret < 0) dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret); diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c index a0f58c3b73f6..60701521c3b1 100644 --- a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c +++ b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c @@ -109,177 +109,140 @@ static inline struct otm8009a *panel_to_otm8009a(struct drm_panel *panel) return container_of(panel, struct otm8009a, panel); } -static void otm8009a_dcs_write_buf(struct otm8009a *ctx, const void *data, - size_t len) -{ - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - - if (mipi_dsi_dcs_write_buffer(dsi, data, len) < 0) - dev_warn(ctx->dev, "mipi dsi dcs write buffer failed\n"); -} - -#define dcs_write_seq(ctx, seq...) \ -({ \ - static const u8 d[] = { seq }; \ - otm8009a_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \ -}) - #define dcs_write_cmd_at(ctx, cmd, seq...) \ ({ \ - dcs_write_seq(ctx, MCS_ADRSFT, (cmd) & 0xFF); \ - dcs_write_seq(ctx, (cmd) >> 8, seq); \ + mipi_dsi_dcs_write_seq_multi(ctx, MCS_ADRSFT, (cmd) & 0xFF); \ + mipi_dsi_dcs_write_seq_multi(ctx, (cmd) >> 8, seq); \ }) static int otm8009a_init_sequence(struct otm8009a *ctx) { struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; /* Enter CMD2 */ - dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01); + dcs_write_cmd_at(&dsi_ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01); /* Enter Orise Command2 */ - dcs_write_cmd_at(ctx, MCS_CMD2_ENA2, 0x80, 0x09); + dcs_write_cmd_at(&dsi_ctx, MCS_CMD2_ENA2, 0x80, 0x09); - dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL, 0x30); - mdelay(10); + dcs_write_cmd_at(&dsi_ctx, MCS_SD_PCH_CTRL, 0x30); + mipi_dsi_msleep(&dsi_ctx, 10); - dcs_write_cmd_at(ctx, MCS_NO_DOC1, 0x40); - mdelay(10); + dcs_write_cmd_at(&dsi_ctx, MCS_NO_DOC1, 0x40); + mipi_dsi_msleep(&dsi_ctx, 10); - dcs_write_cmd_at(ctx, MCS_PWR_CTRL4 + 1, 0xA9); - dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 1, 0x34); - dcs_write_cmd_at(ctx, MCS_P_DRV_M, 0x50); - dcs_write_cmd_at(ctx, MCS_VCOMDC, 0x4E); - dcs_write_cmd_at(ctx, MCS_OSC_ADJ, 0x66); /* 65Hz */ - dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 2, 0x01); - dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 5, 0x34); - dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 4, 0x33); - dcs_write_cmd_at(ctx, MCS_GVDDSET, 0x79, 0x79); - dcs_write_cmd_at(ctx, MCS_SD_CTRL + 1, 0x1B); - dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 2, 0x83); - dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL + 1, 0x83); - dcs_write_cmd_at(ctx, MCS_RGB_VID_SET, 0x0E); - dcs_write_cmd_at(ctx, MCS_PANSET, 0x00, 0x01); + dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL4 + 1, 0xA9); + dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL2 + 1, 0x34); + dcs_write_cmd_at(&dsi_ctx, MCS_P_DRV_M, 0x50); + dcs_write_cmd_at(&dsi_ctx, MCS_VCOMDC, 0x4E); + dcs_write_cmd_at(&dsi_ctx, MCS_OSC_ADJ, 0x66); /* 65Hz */ + dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL2 + 2, 0x01); + dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL2 + 5, 0x34); + dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL2 + 4, 0x33); + dcs_write_cmd_at(&dsi_ctx, MCS_GVDDSET, 0x79, 0x79); + dcs_write_cmd_at(&dsi_ctx, MCS_SD_CTRL + 1, 0x1B); + dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL1 + 2, 0x83); + dcs_write_cmd_at(&dsi_ctx, MCS_SD_PCH_CTRL + 1, 0x83); + dcs_write_cmd_at(&dsi_ctx, MCS_RGB_VID_SET, 0x0E); + dcs_write_cmd_at(&dsi_ctx, MCS_PANSET, 0x00, 0x01); - dcs_write_cmd_at(ctx, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00); - dcs_write_cmd_at(ctx, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00, + dcs_write_cmd_at(&dsi_ctx, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00); + dcs_write_cmd_at(&dsi_ctx, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00, 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00); - dcs_write_cmd_at(ctx, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00, + dcs_write_cmd_at(&dsi_ctx, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00, 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00); - dcs_write_cmd_at(ctx, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00, + dcs_write_cmd_at(&dsi_ctx, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00); - dcs_write_cmd_at(ctx, MCS_NO_DOC2, 0x00); + dcs_write_cmd_at(&dsi_ctx, MCS_NO_DOC2, 0x00); - dcs_write_cmd_at(ctx, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - dcs_write_cmd_at(ctx, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - dcs_write_cmd_at(ctx, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - dcs_write_cmd_at(ctx, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - dcs_write_cmd_at(ctx, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0, + dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0); - dcs_write_cmd_at(ctx, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4, + dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0); - dcs_write_cmd_at(ctx, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - dcs_write_cmd_at(ctx, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - dcs_write_cmd_at(ctx, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25, + dcs_write_cmd_at(&dsi_ctx, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25, 0x00, 0x00, 0x00, 0x00); - dcs_write_cmd_at(ctx, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + dcs_write_cmd_at(&dsi_ctx, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02); - dcs_write_cmd_at(ctx, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, + dcs_write_cmd_at(&dsi_ctx, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - dcs_write_cmd_at(ctx, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26, + dcs_write_cmd_at(&dsi_ctx, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26, 0x00, 0x00, 0x00, 0x00); - dcs_write_cmd_at(ctx, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + dcs_write_cmd_at(&dsi_ctx, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01); - dcs_write_cmd_at(ctx, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, + dcs_write_cmd_at(&dsi_ctx, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 1, 0x66); + dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL1 + 1, 0x66); - dcs_write_cmd_at(ctx, MCS_NO_DOC3, 0x06); + dcs_write_cmd_at(&dsi_ctx, MCS_NO_DOC3, 0x06); - dcs_write_cmd_at(ctx, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, + dcs_write_cmd_at(&dsi_ctx, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, 0x01); - dcs_write_cmd_at(ctx, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, + dcs_write_cmd_at(&dsi_ctx, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, 0x01); /* Exit CMD2 */ - dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF); + dcs_write_cmd_at(&dsi_ctx, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF); - ret = mipi_dsi_dcs_nop(dsi); - if (ret) - return ret; + mipi_dsi_dcs_nop_multi(&dsi_ctx); - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret) - return ret; - - /* Wait for sleep out exit */ - mdelay(120); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); /* Default portrait 480x800 rgb24 */ - dcs_write_seq(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00); - ret = mipi_dsi_dcs_set_column_address(dsi, 0, OTM8009A_HDISPLAY - 1); - if (ret) - return ret; + mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0, OTM8009A_HDISPLAY - 1); - ret = mipi_dsi_dcs_set_page_address(dsi, 0, OTM8009A_VDISPLAY - 1); - if (ret) - return ret; + mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0, OTM8009A_VDISPLAY - 1); /* See otm8009a driver documentation for pixel format descriptions */ - ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT | + mipi_dsi_dcs_set_pixel_format_multi(&dsi_ctx, MIPI_DCS_PIXEL_FMT_24BIT | MIPI_DCS_PIXEL_FMT_24BIT << 4); - if (ret) - return ret; /* Disable CABC feature */ - dcs_write_seq(ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret) - return ret; + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); - ret = mipi_dsi_dcs_nop(dsi); - if (ret) - return ret; + mipi_dsi_dcs_nop_multi(&dsi_ctx); /* Send Command GRAM memory write (no parameters) */ - dcs_write_seq(ctx, MIPI_DCS_WRITE_MEMORY_START); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_MEMORY_START); /* Wait a short while to let the panel be ready before the 1st frame */ - mdelay(10); + mipi_dsi_msleep(&dsi_ctx, 10); - return 0; + return dsi_ctx.accum_err; } static int otm8009a_disable(struct drm_panel *panel) { struct otm8009a *ctx = panel_to_otm8009a(panel); struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; backlight_disable(ctx->bl_dev); - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret) - return ret; + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret) - return ret; - - msleep(120); - - return 0; + return dsi_ctx.accum_err; } static int otm8009a_unprepare(struct drm_panel *panel) @@ -383,6 +346,8 @@ static const struct drm_panel_funcs otm8009a_drm_funcs = { static int otm8009a_backlight_update_status(struct backlight_device *bd) { struct otm8009a *ctx = bl_get_data(bd); + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; u8 data[2]; if (!ctx->prepared) { @@ -397,7 +362,7 @@ static int otm8009a_backlight_update_status(struct backlight_device *bd) */ data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS; data[1] = bd->props.brightness; - otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data)); + mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, data, ARRAY_SIZE(data)); /* set Brightness Control & Backlight on */ data[1] = 0x24; @@ -409,9 +374,9 @@ static int otm8009a_backlight_update_status(struct backlight_device *bd) /* Update Brightness Control & Backlight */ data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY; - otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data)); + mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, data, ARRAY_SIZE(data)); - return 0; + return dsi_ctx.accum_err; } static const struct backlight_ops otm8009a_backlight_ops = { diff --git a/drivers/gpu/drm/panel/panel-samsung-ltl106hl02.c b/drivers/gpu/drm/panel/panel-samsung-ltl106hl02.c new file mode 100644 index 000000000000..1618841b7caa --- /dev/null +++ b/drivers/gpu/drm/panel/panel-samsung-ltl106hl02.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include + +#include